Chapter4 - 47 Chapter 4. CMOS Inverter A CMOS inverter...

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Unformatted text preview: 47 Chapter 4. CMOS Inverter A CMOS inverter consists of an NMOS and a PMOS device connected together using the following topology (drains connected to each other and gates connected to each other). The device consumes zero static power as there is no direct DC path between V DD and GND. CMOS inverter V GSn = V in I Dn = I D V GSp = V in V DD I Dp = I D V DSn = V out V DSp = V out V DD I DSp = -I DSn Although there is no DC current, there will be some current flowing in both devices during the switching of the inverter. Let us consider the static behavior first: Five different regions of operation can be distinguished: 1. NMOS off, PMOS in linear / triode (resistor) regime V DD V DD V out V out R n R p V in = V DD V in = V DD V in = 0 Direct path to ground b V out = 0 Direct path to V DD b V out = V DD V DD V in G S D D S V out C L V D- I D- V GS- V D + I D + V GS + PMOS NMOS 48 2. NMOS turns on (velocity saturation), PMOS still in linear / triode (resistor) regime 3. Both NMOS and PMOS are in velocity saturation regime 4. PMOS turns on (velocity saturation), NMOS in linear / triode (resistor) regime 5. PMOS off, NMOS in linear / triode (resistor) regime See below: CMOS inverter / Static Behavior To find the Switching threshold voltage V M b Both PMOS and NMOS are in velocity saturation. We can write: I DN +I DP = 0 b ignoring channel length modulation 2 2 = --- + -- Dsatp Tp D M Dsatp p Dsatn Tn M Dsatn n V V V V V K V V V V K eq. ( I ) solving for V M r V V V r V V V Dsatp Tp DD Dsatn Tn M + + + + + = 1 2 2 , N satn P satp Dsatn n Dsatp p W W V K V K r = = For large V DD b r rV V DD M + = 1 , r=1 b V M =V DD /2 equal noise margins V out V DD I DN PMOS NMOS V out V in NMOS off PMOS Res NMOS Sat PMOS Res NMOS Sat PMOS Sat NMOS Res PMOS Sat NMOS Res PMOS off 49 For long channel devices b NMOS and PMOS transistors are in saturation and not velocity saturation. Therefore: b V M V T < V Dsat ( I ) in saturation b ) ( ) ( 2 2 = +- +- DD TP M p n T M n V V V K V V K r V V r V V Tp DD Tn M + + + = 1 ) ( , n p K K r- = For 0.25u CMOS with V DD =2.5V ( I ) b 5 . 3 2 / 2 / ' ' / / = + +--- = Dsatp Tp M DD Dsatn Tn M Dsatp Dsat P N N N P P V V V V V V V V n V K K L W L W Sometimes you dont want V M to be in the center. For instance when low input is noisier than high input. In this case it is better to V M closer to V DD . V M 2.5V 1.25V 1 3.4 10 W P /W N V in V out t V in t V out t V out V M n 50 So you adjust (W/L) P /(W/L) N ratio to get non-symmetric V M . But as can be seen from V M figure (see previous page), V M does not change a lot with the ratio....
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This note was uploaded on 09/24/2009 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University-West Lafayette.

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Chapter4 - 47 Chapter 4. CMOS Inverter A CMOS inverter...

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