# Chapter5 - Chapter 5. Combinational Logic In this chapter...

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68 Chapter 5. Combinational Logic In this chapter we learn about various combination logic circuits and how they are implemented using MOS transistors. Our focus throughout this chapter will be still on timing and power dissipation issues. First let us start from the familiar symbols for NAND and NOR gates and their truth tables: NAND NOR First note is that NAND and NOR gates are easy to realize in CMOS (easier than AND, OR). Complementary CMOS Logic is made of a pull-up and a pull-down networks. Its simplest case is an inverter with a PMOS for pull-up and an NMOS for pull-down networks. inverter I 1 I 2 O 0 0 1 0 1 1 1 0 1 1 1 0 I 1 I 2 O 0 0 1 0 1 0 1 0 0 1 1 0 I 1 I 2 O I 1 I 2 O Pull-up network Pull-down network V DD V out A B Pull-up Pull-down

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69 Two input NAND gate can be realized in CMOS as the following: 2 1 I I O = Two input NOR gate can be realized in CMOS as the following 2 1 I I O + = The next question is how to realize a complex function in CMOS logic. Take the following logic function: ) ( C B A D F + + = We first construct the pull-up and pull-down networks using PMOS and NMOS transistors, respectively. Pull-up network Pull-down network I 1 I 2 O 0 0 1 0 1 1 1 0 1 1 1 0 I 1 I 2 O 0 0 1 0 1 0 1 0 0 1 1 0 in1 in2 in1 in2 V DD out Pull-up network Pull-down network V DD out in1 in2 in1 in2 Pull-up network Pull-down network A B C D A B C D
70 Then we put the pull-up and the pull-down networks together: Transfer Characteristic of combinational logic gates Transfer characteristics depends on the data input patterns. Let us study a 2-in NAND gate: b M2 has higher threshold voltage than M1 due to body effect In this case, the gate voltage of top NMOS transistor has to become higher than T DD V V + 2 for the gate to activate output A B C D A B C D Vout V DD A B V DD M2 M1 A B out Internal node No body effect V out V in body effect b Higher V T

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71 Propagation delay of Complementary CMOS gate Propagation delay also depends on the data input pattern b delay = L C Rp 2 69 . 0 b delay = 0.69RpC L b delay = 0.69Rp(C L +C internal node ) For NAND gate to have same pull-down delay(t phl ) as min-sized inverter, NMOS devices must be twice as wide to get same R N and PMOS devices remain unchanged. Widening NMOS increases the capacitance so NAND gate will be always slower than inverter. For NOR gate to be as fast as inverter PMOS devices 2× larger than inverter and NMOS devices remain unchanged. Again widening PMOS increases the capacitance so NOR gates are always slower than inverters. NOR gate b Stacking PMOS slows down the performance of the slow PMOS transistor b NOR gates are generally slower than NAND gates How to account for internal node We use Elmore delay model to analyze the effect of internal nodes: A B A B A=1 B=1 Vout t
72 Assume a 4-input NAND gates t PHL = 0.69(R 1 C 1 +(R 1 +R 2 )C 2 + (R 1 +R 2 +R 3 )C 3 +(R 1 +R 2 +R 3 +R 4 )C L ) b assuming identical NMOS devices and ignore the influence of body effect

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## This note was uploaded on 09/24/2009 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University-West Lafayette.

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Chapter5 - Chapter 5. Combinational Logic In this chapter...

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