Chapter6

Chapter6 - Chapter 6. Sequential logic Defining important...

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92 Chapter 6. Sequential logic Defining important timing parameters Latch vs. Register Level sensitive edge sensitive Static latches and registers b writing data is possible by either cutting the feedback loop or overpowering the feedback loop Clk Clk D Q D Q T t su t hold t c-q Set-up time Propagation delay Data Clock period Data Hold time Combinational logic ins outs Current state next state Q D Clk D Cl Clk Q D Clk Q D Cl Clk Q D Clk Q +ve latch -ve latch +ve edge triggered -ve edge triggered out B Bistable points A in C Metastable(small noise will move the state to either A or B due to gain
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93 Multiplexer-Based latch MUX using NMOS pass transistor using transmission gate Master-Slave Edge-Triggered Register Master Slave 1 0 0 1 D Q M Q Clk Clk -ve latch Holds the data when Clk=1 +ve latch Samples the stable data Q M that is hold -ve latch -ve latch +ve latch +ve latch Q M Q M D D Q Q +ve edge -ve edge -ve latch +ve latch S1 S0 D Clk Clk D S1 S0 Q Q Select Select D D Q Q Clk Clk Clk Q Clk Clk
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94 Timing Properties of MUX-based Master-Slave Register (MS D Flip-Flop) t pd-inv : inverter propagation delay t pd-tx : transmission gate propagation Delay Set-up time: D b Q M t su ( I 1 ,T 1 ,I 3 ,I 2 ) b 3t
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Chapter6 - Chapter 6. Sequential logic Defining important...

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