Chapter9 - Chapter 9. Arithmetic Circuit Adder Circuits A...

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118 Chapter 9. Arithmetic Circuit Adder Circuits A full-adder circuit has three inputs (A, B and Carry in) and two outputs (sum and carry out). Full adder i i i i i i i AC BC AB C ABC C B A C B A C B A C B A S + + = + + + = = 0 One can make a ripple carry adder using the following circuit. Propagation delay of an N-bit adder is set by the delay in generating carries from N-1 stages and the delay to generate the sum for the last stage. sum carry adder t 1)t - (N t + = A B C i S C 0 b carry goes to the next bit A1 B1 A2 B2 A3 B3 C1 S1 C2 S2 S3 C3 b Ripple carry adder A B C i C i A A A A A A A B B B B B B B C i C i C i C i V DD V DD 0 C 0 C S
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119 b Compared to A and B, Carry-in Ci is always critical path so the Ci path needs to be as close as possible to the output to reduce propagation delay. ) ( 0 0 i i i i C B A C ABC S AC BC AB C + + + = + + = The ripple carry adder implemented with CMOS logic requires: large area (due to multiple transistors and complex interconnect) PMOS stack b which makes the circuit very slow Carry generation needs two gates Note that minimizing the carry generation path is important as seen by the propagation delay equation. Sum generation also needs an extra inverter gate but that is not as important since it appears only once in the delay equation of ripple carry adder. Tricks to improve the performance
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This note was uploaded on 09/24/2009 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University-West Lafayette.

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Chapter9 - Chapter 9. Arithmetic Circuit Adder Circuits A...

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