Chapter10

Chapter10 - Chapter 10. Memory Architectures Memory Timing...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
126 Chapter 10. Memory Architectures Memory Timing Parameter Definitions Read cycle Write cycle Read Write read access valid data write access Data is written Memory classification RWM: Read/Write Memory NVRWM: Non-Volatile Read/Write Memory ROM: Read-Only Memory SRAM: Static Random Access Memory DRAM: Dynamic Random Access Memory FIFO: First in First out FILO: First in Last out CAM: Contents Addressable Memory RWM NVRWM ROM Random access Non-random access EPROM Mask-programmed SRAM FIF0 E 2 PROM Programmable (PROM) DRAM LIF0 Flash Shift Reg. CAM
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
127 Bit line Array organization 2 L-k A k Row decoder A L-1 Sense Amp/Driver M.2 K Word line Storage cell Column decoder I/O (M-bits) A 0 A k-1 Let us look at the architecture of N-word memory (N could be 2G-byte ~ 2 31 ) where each word is M bits wide (M could be 32 bits, 2 8 ). Only one word at a time is selected for reading or writing with the aid of a select bit. We use decoders to reduce the number of address bits as only one word in the memory is selected at any given time. The address bus is divided into lines that go to column and row decoders. Note that since memories are very asymmetric (2 31 byte vs 2 8 bit), one usually design several bytes in one row. This makes the layout of the memory symmetric and also reduces the length of interconnects. The column and row decoders apply word line and bit line to the storage cell. The row address enables one row of the memory for R/W operation (this goes to several words) while the column address picks one particular word from the selected row. For the read operation the output of the cell that is selected is detected by sense amplifiers. For write operation, driver writes the data into the storage cell.
Background image of page 2
Memory Core BL BL V DD WL WL V DD V DD BL WL WL MOS ROM1 MOS ROM2 BL0 BL1 V DD WL0 Pull up devices WL1 WL0 Pseudo-NMOS V bias NOR WL1 NOR MOS Pull down devices The memory core ROM : read-only memory The contents of ROM cells are permanently fixed, so only read operation is possible. 0 or 1 is presented to the bit line (BL) upon activation of its word line (WL). Data read = 1 Data read = 0 In the layout mirroring of the odd cells is used to share Vdd line between adjacent memory cells. That would make the structure more compact. Also, instead of resistors we use NMOS pull-down devices in MOS ROM1 implementation or PMOS pull-up devices in MOS ROM2 implementation. MOS ROM1 can implement an OR logic if two or more WL’s activate a common BL.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 10

Chapter10 - Chapter 10. Memory Architectures Memory Timing...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online