This preview shows pages 1–2. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: EE456 HW2 solutions 1 EE456 HW2 Solutions Problem 1. a) I D =0, V D =-V S =-3.3V [more exact: I D = I REV = -I S , V D = -(V S-I S R S )] b) Reversed biased c) ( ) D o D A D A si j V N N N N q W + = 2 q=1.6x10-19 C, V D = -V S =-3.3V, si =11.7 o =1.035x10-12 F/cm, N A =2.5x10 16 cm-3 , N D =5x10 15 cm-3 W j =110.043x10-6 cm d) j D si j W A C = , with A D =12x10-8 cm 2 , C j =1.129fF e) V S NEW =1.5V < V S OLD =3.3V The new voltage reduces the reverse bias of the PN junction, hence the width of the depletion region, W j , decreases. As you bring the plates of a capacitor together, the capacitance increases. Problem 2. a) This is a PMOS device from the measurement table. For example, when V GS > 0 I D =0, and when V GS <0 I D 0. For solving b) c) d), using In velocity saturation, ( ) ( ) DS DSAT DSAT t GS D V V V V V L W k I + = 1 2 2 ' b) Using measurement 1 and 4, ( ) ( ) ( ) ( ) 5 . 2 1 2 ) 1 ( 1...
View Full Document
- Spring '09
- Integrated Circuit