# HW3 - L g Do high or low impedance loads seem to produce...

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EE456 HW3 Due date: Feb 5 th 1 Figure 1 shows an NMOS inverter with resistive load. Use 0.25um TSMC 2.5V CMOS model parameters, i.e., for NMOS, VT0=0.456V, UO=0.0339m 2 /Vs, and TOX=5.8e-9m. a. Qualitatively discuss why this circuit behaves as an inverter. b. Calculate V OH , V OL , V IH , V IL , V M , NM H , and NM L . c. Compute the average power dissipation for: (i) Vin= 0 V and (ii) Vin= 2.5 V d. Plot the VTC using HSPICE of CADENCE and indicate V OH , V OL , V IH , V IL , V M , NM H , and NM L . e. Use HSPICE of CADENCE to sketch the VTCs for R L = 37.5k, 75k, and 150k on a single graph. f. Comment on the relationship between the critical VTC voltages (i.e., V OH , V OL , V IH , V IL ) and the load resistance, R
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Unformatted text preview: L . g. Do high or low impedance loads seem to produce more ideal inverter characteristics? Figure 1. Resistive-load inverter Hints for Cadence: In order to plot the VTC using HSPICE of CADENCE, use DC analysis. It will be better to use the ‘vdc’ symbol in the library of ‘analogLib’ instead of ‘input pin’ and ‘stimulus’ in order to make the input signal of Vin. Also in order to sketch the VTCs for R L = 37.5k, 75k, and 150k on a single graph, it will be helpful to use the value of RL as ‘Design Variable’ instead of ‘75k’ and use the ‘Parameter Analysis’ tool in Affirma Analog Circuit Design Environment....
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