HW4-solution - that’s at least a few hundred nanometers...

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EE456 HW4 - SOLUTIONS 1.) i) W = 1.2 u L= 0.3 u IV Characteristics (NMOS)
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ii) W = 4.8 u L = 0.6 u IV Characteristics (NMOS)
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iii) W = 1.2 u L= 0.3 u IV Characteristics (PMOS)
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iii) W = 4.8 u L= 0.6 u IV Characteristics (PMOS) Problem 1-2. Indicate on the plots from problem 1-1. a. the regions of operation. These are shown in the plots. b. Comment on the effect of channel length modulation as observed in the plots. Channel length modulation can be observed in all the samples, as the increase of the drain current with increasing drain voltage. If we look closely, however, we observe that channel length modulation is more pronounced in shorter channels ( L = 300 nm vs. L = 600 nm). This is indeed what we expect because as the channel length is scaled, the drain terminal depletes the inverted carriers across the channel, decreasing the effective channel length. This in return increases the current because the channel resistance is reduced ( R ~ 1/L – Ohm’s Law , for L
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Unformatted text preview: that’s at least a few hundred nanometers long) c. Which of the devices are in velocity saturation? Explain how this can be observed on the IV plots. We can approximate the devices that are operating in the velocity saturation region, by noting the gate voltage behavior with respect to transistor current. For long channel devices, transistor current is proportional to the square root of the gate voltage . Therefore the spacing between VDS sweeps for different gate voltages should gradually increase. This is indeed almost what we observe for the long channel devices in the plots shown above. For short channel devices however, the current is no longer proportional to the square of the gate voltage, hence, the spacing between VDS sweeps for different gate voltages is equal. Our short channel outputs are good examples....
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