HW5 - EE456 HW5 Due date: Feb 19th EE456 HW5 (Note: This HW...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
EE456 HW5 Due date: Feb 19 th EE456 HW5 (Note: This HW has double the weight of previous HWs) Problem 1. (3pts). For following inverter, find the trip point voltage (the input voltage for which Vin=Vout). Use the following conditions. VDD=5V, Vtn=1V, Vtp=-1V, un/up=2, (W/L)n=(W/L)p. VDD Vout Vin Figure P1. Pseudo-NMOS inverter. Problem 2. (7pts). In this exercise, you are going to investigate some interesting design considerations in transistor sizing. Suppose that you are given an inverter with NMOS transistor having a minimum length/width and a PMOS transistor with variable width and minimum length. Make appropriate simulations using SPICE with the available technology files and answer the following questions: i) Find the optimum PMOS width that produces the minimum propagation delay possible. ii) Why can’t we simply push the PMOS width to colossal lengths to minimize the total delay? Argue. iii)
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 09/24/2009 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University-West Lafayette.

Ask a homework question - tutors are online