HW5-solution

HW5-solution - EE 456 HOMEWORK 5 SOLUTIONS Problem 2. i)...

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EE 456 – HOMEWORK 5 – SOLUTIONS
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Problem 2. i) Find the optimum PMOS width that produces the minimum propagation delay possible. Perfoming the detailed parametric simulation in the homework assignment, we could plot the output low-to-high, and output high-to-low times (t plh and t phl ) with respect to changing PMOS Width. On the right hand side in Figure-1, you see the transient reponse of the inverter for a periodic input pulse for different W’s. On the left hand side, you see the output low-to-high and output high-to-low values. We see that the optimum W is around 1.3 um for the PMOS when the NMOS width is 450 nm (minimum). Here we assumed a relatively low output capacitance to prevent a dominating effect due to the added capacitance. Cadded = 1 f F. Figure 1 Low-to-High and High-to-Low transition delays and transient response
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ii) Why can’t we simply push the PMOS width to colossal lengths to minimize the total delay? Argue. We can’t irresponsibly increase the PMOS width because this degrades our high-to-low
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HW5-solution - EE 456 HOMEWORK 5 SOLUTIONS Problem 2. i)...

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