This preview shows page 1. Sign up to view the full content.
EE456 HW6
Due date: Feb 24
th
1
EE456 HW6
Problem1 (2 points):
Implement the following logic functions with minimum number of transistors in complementary CMOS
logic. Specify transistor widths next to each transistor to achieve maximum speed:
1
(
)
F
A B C
AB
=
⋅
+
+
2
F
A B C D
=
⋅
+
⋅
3
F
A B C
A
=
⋅
⋅
+
4
F
A B C
=
+
⋅
Problem2 (3 points):
Assuming an optimum
W
p
/W
n
ratio of 3, design the following circuits in complementary CMOS logic such
This is the end of the preview. Sign up
to
access the rest of the document.
Unformatted text preview: that the delay in the critical path A > X is minimized. Calculate branching effort, logic effort and electrical effort of each gate according to the W p /W n ratio specified here. Assume that the gate capacitance of an inverter with minimum size W n =0.25μm and W p =0.75μm is 4fF. X C L A = 1pF A X C L = 2pF...
View
Full
Document
This note was uploaded on 09/24/2009 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue UniversityWest Lafayette.
 Spring '09
 Mohammadi
 Integrated Circuit, Transistor

Click to edit the document details