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ECE456 HW8
Due date: March. 26
th
EE456 HW8
Problem 1.
Consider the four-input NAND gate below, where the internal capacitance equals 2 fF, the load
capacitance is 24fF, and the top three transistors (A, B, and C) of the PDN are enabled while transistor D is off.
a)
Find the voltage drop at Vout under these conditions.
b)
Implement two different methods to modify the circuit (draw the schematic for each new implementation)
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Unformatted text preview: to eliminate the charge sharing problem. V V DD 5 = P M φ out V t C a C b C c C d C a M b M c M d M N M GND = D C B A V 5 V Problem 2. Draw the circuit diagram that implements the following functions using (a) static CMOS, (b) n-Domino CMOS (c) True single phase with latched output. (a) 1 ( ).( ) F D E A B C = + + + (b) 2 . . . . . . . . F A B C A B C A B C A B C = + + + (c) 3 . . . F A B A B C = +...
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- Spring '09
- Mohammadi
- Gate, Integrated Circuit, Transistor, Trigraph, Logic gate, Circuit diagram
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