HW9-solution - block circuit diagram in Cadence(Note the...

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EE456 HW9-SOLUTIONS Problem 1 a-) Block diagram:
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Solution Strategy : We need to be able to switch between serial-in and parallel-in, we need a chain of flip flops to store the serial information. For parallel loading, we need to wire all the inputs to the inputs of the DFF’s. The 2x1 multiplexers select the input data if select signal is 1, otherwise they select the output of the individual flip flops to transfer serial input. The implementation of the MUX is given above. b-) We are going to use a True Single Phase Clock Register (TSPC) in this design. The main reasons are that its operation principle is simple, it is compatible with standard cell design, it is static, and it requires a few transistors. We could use minimum transistor lengths for the NMOS transistors and two times the
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NMOS widths for PMOS transistors. If the CLOCK signal is sufficiently steep, there is no practical danger in using TSPC. For further information, see Rabaey (2001), Section 7.3.3. Below is a snapshot of the final
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Unformatted text preview: block circuit diagram in Cadence: (Note the buffer in the middle to prevent overloading the nodes in this HP design) c-) Plots are attached below: Select/ ABCD 1 1111 S=1 , Q1,Q2,Q3,Q4=1111 after ONE clock cycle (CLK not shown) Select/ ABCD 1 1011 S=1 , Q1,Q2,Q3,Q4=1011 after ONE clock cycle (CLK not shown) Select/ ABCD 1 0000 S=1 , Q1,Q2,Q3,Q4=0000 after ONE clock cycle (CLK not shown) Select/ ABCD 0 1101 (Serial Input = D1) At the end of 4-clock cycles the MSB (D4 in our waveforms) must be 1, D3 must be 1, D2 must be 0 and D1 must be 1. Because the MSB will be D4, we must apply the input in a reversed fashion (D_serial = 1011 in this case) Marker shows that at 40ns we have Q4,Q3Q2,Q1=1101 Select/ ABCD 0 1000 (Serial Input = D1) We clearly see that the input propagates to Q4, and at 40 ns the data is ready to be sampled in parallel. The last test case can be analyzed similarly....
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