EE456 HW10
Due: April 30
th
2009
EE456 HW10
(Note: This HW has triple weight + additional bonuses)
In this homework, you are going to design a
16bit pipelined KoggeStone adder
to be used in
the accumulator portion of a high performance chip for the company you are working for. Before
going into the details regarding the method of pipelining, you need to familiarize yourself with
the PropagateGenerate notation that is commonly used in parallel prefixtree adders.
Theory:
(i)
Using PG (PropagateGenerate) notation (see below)
obtain
an expression for P
7:0
and G
7:0
in
terms of
P
0:0
and G
0:0
.
(ii)
Describe
in words how the propagate and generate signals recursively help to produce the
output in a prefix adder.
(iii)
Pipelining:
Pipelining is a general architectural technique that is widely used in high
performance/throughput systems. In circuits, pipelining is achieved by inserting register elements
in the design such that the critical paths of the partitions are almost equal. (
Discuss why
this is a
very important requirement). In the literature, two methods of pipelining adders have been
reported. We are going to call these
horizontal
and
vertical
pipelining schemes. One way to
partition an adder is to break the word length (16bits) into two (8bits) and insert the register
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 Spring '09
 Mohammadi
 Integrated Circuit, KoggeStone adder, KS Adder, horizontal pipelining scheme

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