HW10-AdderPaper - A Taxonomy of Parallel Prefix Networks David Harris Harvey Mudd College Sun Microsystems Laboratories 301 E Twelfth St Claremont

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A Taxonomy of Parallel Prefix Networks David Harris Harvey Mudd College / Sun Microsystems Laboratories 301 E. Twelfth St. Claremont, CA 9171 1 David [email protected] Abstract - Parallel prefu networks are widely used in high- performance adders. Networks io the Literature represent tradeoffs between number of logic levels, fanout, and wiring tracks. This paper presents a three-dimensional taxonomy that not only describes the tradeoffs in existing parallel pretix networks but also points to a family of new networks. Adders using these networks are compared using the method of logical effort. Tbe new architecture is competitive in latency and area for some technologies. I. INTRODUCTION A parallel prefvt circuit computes N outputs {YN, . . ., K} fromNinputs (X, ..., XI} using anarbitrary associative two-input operator o as follows [13] r, = XI r, =x, ox, r, =X,OX*~X, rN=xNox, Io. ..ox,~x, Common prefix computations include addition, incrementation, priority encoding, etc. Most prefvr computations precompute intermediate variables ~N:N, . . Z,:,] from the inputs. The preh network combines these intermediate variables to form the prefixes (ZM~, ZM}. The outputs are postcomputed from the inputs and prefixes. For example, adders take inputs VN, AI}, {BN, BI} and C, and produce a sum output {SN, ___, SI} using intermediate generate (G) and propagate (P) prefvr signals. The addition logic consists of the following calculations and is shown in Fig. 1. - G,, = 4.B, . Go, = C,, Precomputation: (2) c,=4 B,’P,,=O Prefix: Postcomputation: S, =P, G, ,9 (4) There are many ways to perform the prefix computation. For example, serial-prefix shuctures like ripple carry adders are compact but have a latency O(N). Single-level carry lookahead structures reduce the latency by a constant factor. Parallel prefm circuits use a tree network to reduce latency to Rd-Wuam c, s. 8, s, Fig. Pmfi. computation: 4-bk dda O(log N) and widely used in fast adders, priority encoders p], and other prefvt computations. This paper focuses on valency-2 prefvt operations (i.e. those that use 2-input associative operators), but the results readily generalize to higher valency [I]. Many parallel prefix networks have been described in the literature, especially in the context of addition. The classic networks include Brent-Kung [2], Sklansky [I 11, and Kogge-Stone [SI. An ideal prefix network would have lo&N stages of logic, a fanout Ever exceeding 2 at each stage, and no more than one horizontal track of wire at each stage. The classic architectures deviate from ideal with 2log2N stages, fanout of N/2+l, and N/2 horizontal tracks, respectively. The Han-Carlson family of networks [SI offer tradeoffs in stages and wiring between Brent-Kung and Kogge-Stone. The Knowles family [7] similarly offers tradeoffs in fanout and Wiring between and Kogge- Stone and the Ladner-Fischer family [IO] offers tradeoffs
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This note was uploaded on 09/24/2009 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University-West Lafayette.

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HW10-AdderPaper - A Taxonomy of Parallel Prefix Networks David Harris Harvey Mudd College Sun Microsystems Laboratories 301 E Twelfth St Claremont

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