Lecture_6 - Lecture 6: Building Single-Cycle Datapath and...

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Lecture 6: Building Single-Cycle Datapath and Control Unit 1
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How to Design a Processor: step-by-step ± 1. Analyze instruction set => datapath requirements – the meaning of each instruction is given by the register transfers – datapath must include storage element for ISA registers – datapath must support each register transfer ± 2. Select set of datapath components and establish clocking methodology ssemble atapath meeting the requirements ± 3. Assemble datapath meeting the requirements ± 4. Analyze implementation of each instruction to determine tting of control points that effect the register transfer setting of control points that effect the register transfer. ± 5. Assemble the control logic 2
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Step 1: The MIPS-lite Subset for today ± ADD and SUB – addU rd, rs, rt ubU rd rs rt p s t d hamt unct 0 6 11 16 21 26 31 – subU rd, rs, rt ± OR Immediate: – ori rt, rs, imm16 op rs rt rd shamt funct 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits ± LOAD and STORE Word – lw rt, rs, imm16 w rt rs imm16 op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits sw rt, rs, imm16 ± BRANCH: – beq rs, rt, imm16 p arget address 0 26 31 – jump op target address 6 bits 26 bits 3
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Execution Flow Instruction Fetch add c, a, b sub d, a, c Instruction ecode add d, c, d . . Decode + Operand a+b memory . Fetch Execute a b Result Store gister c Next Instruction 4 register
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Instruction <=> Register Transfers ± RTL (Register Transfer Languages) gives the meaning of the instructions ± All start by fetching the instruction yg op | rs | rt | rd | shamt | funct = MEM [ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers ADDU R [rd] <– R [rs] + R [rt]; PC <– PC + 4 SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ORi R[rt] <– R[rs] + zero_ext (Imm16); PC <– PC + 4 LOAD R[rt] <– MEM[ R[rs] + sign_ext (Imm16)]; PC <– PC + 4 STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4 BEQ if ( R[rs] == R[rt] ) then PC <– PC + 4 sign ext(Imm16 5 +sign_ext(Imm16 )] else PC <– PC + 4
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Step 1: Requirements of the Instruction Set ± Memory struction & data instruction & data ± Registers (32 x 32) r ad RS ead S – read RT – Write RT or RD ± PC ± Extender ± Add and Sub register or extended immediate ± Add 4 or extended immediate to PC 6
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Step 2: Components of the Datapath ± Combinational Elements –The outputs only depend on the current inputs. –Example: ALU ± Storage Elements (state element) –The outputs depend on both their inputs and the contents of the internal state. –At least two inputs and one output Inputs input data and clock (clocking methodology) Output the value stored in a state element –Example: D Flip-Flop, register and memory 7
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Clocking Methodology ± Define when signals can be read and when they can be written ± Edge-triggered clocking – All state changes occur on a clock edge. ctive edge – Active edge • Rising edge or Falling edge – No feedback in the same clock cycle • A state element could be read/written in the same clock cycle 8
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Combinational Logic Elements (Basic Building Blocks) arryIn ± Adder 32 A 2 Sum Ad d CarryIn 32 B 32 Carry er ± MUX Select LU 32 A B 2 Y 32 MUX ± ALU O 3 32 A 32 Result P ALU 9 32 B
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Lecture_6 - Lecture 6: Building Single-Cycle Datapath and...

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