Lecture_7 - Lecture 7 Multicycle Implementations...

Lecture 7
ulticycle Implementations Multicycle Implementations
1

Review: Single Cycle Implementations
2

What’s wrong with our CPI=1 processor?
Reg File Inst Memory
ALU
Arithmetic & Logical
Reg File
Inst Memory
ALU
Data Mem
Reg File
Load
ritical Path
Reg File
Inst Memory
ALU
Data Mem Reg File
Store
Critical Path
Inst Memory ALU Reg File
Branch
±
Long Cycle Time
±
All instructions take as much time as the slowest
±
Real memory is not so nice as our idealized memory
annot always get the job done in one (short) cycle
3
– cannot always get the job done in one (short) cycle

Multiple Cycle Processor
±
Break the instruction into smaller steps
±
Execute each step (instead of the entire instruction) in 1 clock
ycle cycle
– Cycle time: time it takes to execute the longest step
– Try to make all the steps have similar length
±
The advantage of the multiple cycle processor:
– Cycle time is much shorter
– Different instructions take different number of cycles to complete yp
– Allow a functional unit to be used more than once per instruction
4

High-Level View of Multiple Cycle Datapath
IR
PC Address
Instruction
register
Data
Register#
A
Memory
or data
Registers
Register #
g
ALU
data
B
ALUOut
MDR
1. A single memory unit is used for both instructions and data.
2. There is a single ALU.
3. One or more registers are added after every major functional unit
-- hold the output of that unit until the value is used in a subsequent clock
cle
5
cycle

Five Execution Steps
±
Instruction Fetch
±
struction Decode and Register Fetch Instruction Decode and Register Fetch
±
Execution, Memory Address Computation, or Branch
Completion
±
Memory Access or R-type instruction completion
±
Write-back step
INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!
6

Step 1: Instruction Fetch
±
Use PC to get instruction and put it in the Instruction Register.
±
Increment the PC by 4 and put the result back in the PC.
±
Can be described succinctly using RTL "Register-Transfer Language"
IR = Memory[PC];
PC = PC + 4;
7

Step 1: Instruction Fetch
PCWr = 1
QUAL
PCWrCond PCSrc=0
<< 2
IR[25-0]
PC[31-28]
:
MemWr = 0
32
IRWr= 1 RegWr
ALUSelA=0
RegDst
PC
1
EQUAL
IorD = 0
2
RAdr
A
L
Instru
c
2
32
Ra
Rb
5
busA
Rs
Rt
Mu
x
0
32
Mux
0
1
32
0
Equal
2
AL
U
A
Ideal
Memory
WrAdr
Din
32
32
Dout
32
32
tion Reg
32
Reg File
Rw
busW
5 32
3
busB
0
Rt
Rd
1
0
1
4
32
Out
B
32
ALU
Control
2
1
Mux
0 1
2
3
<< 2
Memory data
register
ALUOp=ADD
Extend
16
Imm
32
MemRead = 1
8
MemtoReg ExtOp ALUSelB=01

Step 2: Instruction Decode and Register Fetch
±
Read registers rs and rt in case we need them
±
Compute the branch address in case the instruction is a branch
TL:
±
RTL:
A = Reg[IR[25-21]];
Reg[IR[20 6]]; B = Reg[IR[20-16]];
ALUOut = PC + (sign-extend(IR[15-0]) << 2);
R-type instruction: register -register
Op
6
rs rt
shamt
55
5
rd
56
funct
I-type instruction : register - immediate
65 5
16
9
Op rs rt
Immediate

Step 2: Instruction Decode and Register Fetch
PCWr
qual
PCWrCond PCSrc
<< 2
IR[25-0]
PC[31-28]
:
MemWr
32
IRWr RegWr
ALUSelA= 0
RegDst
PC
1
Equal
IorD
2
RAdr
A
L
Instru
c
2
32
Ra
Rb
5
busA
Rs
Rt
Mu
x
0
32
Mux
0
1
32
0
Equal
2
AL
U
A
Ideal
Memory
WrAdr
Din
32
32
Dout
32