lecture_8_new - Lecture 8 Pipelining 1 Pipelining is...

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Lecture 8 Pipelining pg 1
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Pipelining is Natural! ± Laundry Example ± Ann, Brian, Cathy, Dave each have one load of clothes A B C D to wash, dry, and fold ± Washer takes 30 minutes ± Dryer takes 30 minutes ± Folder takes 30 minutes ± Putting clothes into drawers takes 30 minutes 2
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Sequential Laundry 6 PM 7 8 9 10 11 12 1 2 AM 30 T Time 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 a s k B A O C D r d e ± Sequential laundry takes 8 hours for 4 loads they learned pipelining how long would laundry take? r 3 ± If they learned pipelining, how long would laundry take?
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Pipelined Laundry: Start work ASAP 12 2 AM 6 PM 7 8 9 10 11 1 T a Time A 30 30 30 30 30 30 30 s k B O C D r d e ± Pipelined laundry takes 3.5 hours for 4 loads! r 4
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Pipelining Lessons ± Pipelining doesn t help latency of single task, it 6 PM 78 9 helps throughput of entire workload Time 30 30 30 30 30 30 30 T a ± Multiple tasks operating simultaneously using ifferent resources A s k different resources ± Pipeline rate limited by lowest ipeline stage B C O slowest pipeline stage ± Unbalanced lengths of ipe stages reduces D r d e pipe stages reduces speedup r 5
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The Five Stages of Load Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Ifetch Reg/Dec Exec Mem Wr Load ± Ifetch: Instruction Fetch – Fetch the instruction from the Instruction Memory ± Reg/Dec: Registers Fetch and Instruction Decode ± Exec: Calculate the memory address ± Mem: Read the data from the Data Memory ± Wr: Write the data back to the register file 6
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Pipelining ± Improve performance by increasing instruction throughput Instruction fetch Reg ALU Data access Time lw $1, 100($0) 2 4 6 8 10 12 14 16 18 Program execution order (in instructions) 8 ns Instruction fetch Data access Instruction fetch lw $2, 200($0) lw $3, 300($0) ... 8 ns 2 4 6 8 14 Time Program (in instructions) Instruction fetch Reg ALU Data access Reg lw $1, 100($0) lw $2, 200($0) lw $3, 300($0) 2 ns Instruction fetch Reg ALU Data access 2 ns Instruction Reg ALU Time to execute 4 load instructions: fetch access 2 ns 2 ns 2 ns 2 ns 2 ns 7 Single cycle: 8 x 4 = 32 ns Pipeline: 4 x 1 + 4 (time to drain the pipeline) = 8 Cycle = 16 ns
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Single Cycle, Multiple Cycle, vs. Pipeline Clk Single Cycle Implementation : Cycle 1 Cycle 2 Load Store Waste Clk Cycle 1 Multiple Cycle Implementation : Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Load Store R-type Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem Pipeline Implementation: Ifetch Load Ifetch Reg Exec Mem Ifetch Reg Exec Mem Store 8 Ifetch Reg Exec Mem R-type
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Ideal Pipeline Performance ± Ideal CPI = 1 ime to execute n instruction ± Time to execute n instruction – 1 x n + time to drain the pipeline Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem Ifetch Reg Exec Mem ± Ideal speedup from pipelining == # of pipeline stages – If the stages are perfectly balanced, and a large number of structions instructions Time between instructions ipelined = Time between instructions onpipelined 9 pipelined nonpipelined Number of pipe stages
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Graphically Representing Pipelines CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 Time (in clock cycles) Program
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lecture_8_new - Lecture 8 Pipelining 1 Pipelining is...

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