lecture_8_new - 1 Lecture 8 Pipelining 2 Pipelining is...

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Unformatted text preview: 1 Lecture 8 Pipelining 2 Pipelining is Natural! Laundry Example Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Dryer takes 30 minutes Folder takes 30 minutes Putting clothes into drawers takes 30 minutes A B C D 3 Sequential Laundry Sequential laundry takes 8 hours for 4 loads If they learned pipelining, how long would laundry take? 30 T a s k O r d e r B C D A Time 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 6 PM 7 8 9 10 11 12 1 2 AM 4 Pipelined Laundry: Start work ASAP Pipelined laundry takes 3.5 hours for 4 loads! T a s k O r d e r 12 2 AM 6 PM 7 8 9 10 11 1 Time B C D A 30 30 30 30 30 30 30 5 Pipelining Lessons Pipelining doesnt help latency of single task, it helps throughput of entire workload Multiple tasks operating simultaneously using different resources Pipeline rate limited by slowest pipeline stage Unbalanced lengths of pipe stages reduces speedup 6 PM 7 8 9 Time B C D A 30 30 30 30 30 30 30 T a s k O r d e r 6 The Five Stages of Load Ifetch: Instruction Fetch Fetch the instruction from the Instruction Memory Reg/Dec: Registers Fetch and Instruction Decode Exec: Calculate the memory address Mem: Read the data from the Data Memory Wr: Write the data back to the register file Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Ifetch Reg/Dec Exec Mem Wr Load 7 Pipelini ng Improve performance by increasing instruction throughput Time to execute 4 load instructions: Single cycle: 8 x 4 = 32 ns Pipeline: 4 x 1 + 4 (time to drain the pipeline) = 8 Cycle = 16 ns Instruction fetch Reg ALU Data access Reg 8 ns Instruction fetch Reg ALU Data access Reg 8 ns Instruction fetch 8 ns Time lw $1, 100($0) lw $2, 200($0) lw $3, 300($0) 2 4 6 8 10 12 14 16 18 2 4 6 8 10 12 14 ... Program execution order (in instructions) Instruction fetch Reg ALU Data access Reg Time lw $1, 100($0) lw $2, 200($0) lw $3, 300($0) 2 ns Instruction fetch Reg ALU Data access Reg 2 ns Instruction fetch Reg ALU Data access Reg 2 ns 2 ns 2 ns 2 ns 2 ns s Program execution order (in instructions) 8 Single Cycle, Multiple Cycle, vs. Pipeline Clk Cycle 1 Multiple Cycle Implementation : Ifetch Reg Exec Mem Wr Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Load Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem Load Store Pipeline Implementation: Ifetch Reg Exec Mem Wr Store Clk Single Cycle Implementation : Load Store Waste Ifetch R-type Ifetch Reg Exec Mem Wr R-type Cycle 1 Cycle 2 9 Ideal Pipeline Performance Ideal CPI = 1 Time to execute n instruction 1 x n + time to drain the pipeline Ideal speedup from pipelining == # of pipeline stages If the stages are perfectly balanced, and a large number of instructions Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem Wr Time between instructions pipelined = Time between instructions nonpipelined Number of pipe stages 10 Graphically Representing Pipelines...
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lecture_8_new - 1 Lecture 8 Pipelining 2 Pipelining is...

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