Lecture_9 - Lecture 9: Pipelining (II) 1. Data Hazards and...

Info iconThis preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon
Lecture 9: Pipelining (II) 1. Data Hazards and Forwarding 2. Control Hazard Solution . How to Handle Exception 3. How to Handle Exception 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Datapath with Control Control M WB P C S r c ID/E X EX/MEM MEM/WB M u x 0 1 Add Branch ALUSrc 4 result Shift left 2 RegWrite EX M IF/ID Write PC In stru c tio n memory Instruction MemtoReg 0 0 Registers Wr i te register i data Read data 1 data 2 register 1 register 2 M u x 1 ALU Zero i M u x 1 Mem Address Data [20– 16] ALUOp 16 32 [15– 0] M u x 0 Sign extend d a ta control MemRead [15– 11] 6 RegDst 1 H t i l t “d t f di ”? 1. How to implement “data forwarding”? 2. How to detect load-use hazard? How to stall pipeline? How to resolve branch in the decode stage? 2 3. How to resolve branch in the decode stage? 4. How to flush pipeline?
Background image of page 2
Data Dependence Detection & Forwarding ime (clock cycles) CC1 CC2 CC3 CC4 CC5 CC6 Time (clock cycles) sub r2 ,r1,r3 ALU Im Reg Dm Reg I n s t and r12, r2 ,r5 Im Reg Dm Reg r. O or r13,r6, r2 Im Reg Dm Reg A r d e add r14, r2 ,r2 Im LU Reg Dm Reg L m eg r sw r15, 100($r2) U Im Reg Dm Reg 3
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
How to detect dependency between (sub, and)? Time (clock cycles) A CC1 CC2 CC3 CC4 CC5 CC6 I n sub r2 ,r1,r3 nd r12 5 LU Im Reg Dm Reg L eg m eg s t r. and r12, r2 ,r5 r r13,r6, U Im Reg Dm Reg AL Im Reg Dm Reg O r d or r2 add r14, r2 ,r2 Im ALU Reg Dm Reg e r sw r15, 100($r2) Im Reg Dm Reg a: EX/MEM RegisterRd = ID/EX RegisterRs 4 1a: EX/MEM. RegisterRd = ID/EX.RegisterRs 1b: EX/MEM. RegisterRd = ID/EX.RegisterRt
Background image of page 4
How to detect dependency between (sub, or)? Time (clock cycles) A CC1 CC2 CC3 CC4 CC5 CC6 I n sub r2 ,r1,r3 nd r12 5 LU Im Reg Dm Reg L eg m eg s t r. and r12, r2 ,r5 r r13,r6, U Im Reg Dm Reg AL Im Reg Dm Reg O r d or r2 add r14, r2 ,r2 Im ALU Reg Dm Reg e r sw r15, 100($r2) Im Reg Dm Reg 2a: MEM//WB.RegisterRd = ID/EX.RegisterRs (sub & or) 5 2b: MEM/WB.RegisterRd = ID/EX.RegisterRt
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Data Dependence Detection (cont.) ± Hazard conditions: – 1a: EX/MEM. RegisterRd = ID/EX.RegisterRs (sub & and) – 1b: EX/MEM. RegisterRd = ID/EX.RegisterRt a: MEM/WB.RegisterRd = ID/EX.RegisterRs (sub & or) 2a: MEM/WB.RegisterRd ID/EX.RegisterRs (sub & or) – 2b: MEM/WB.RegisterRd = ID/EX.RegisterRt – RegWrite signal of WB Control field • EX/MEM.RegWrite, MEM/WB.RegWrite – EX/MEM.RegisterRd <> $0 EM/WB RegisterRd <> $0 – MEM/WB.RegisterRd <> $0 How to forward data? 6
Background image of page 6
Resolving Hazards by Forwarding ± Use the value in pipeline registers rather than waiting for the WB tage to write the register file. stage to write the register file. CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 Time (in clock cycles) CC 7 CC 8 CC 9 Program 10 10/– 20 – 20 Value of register $2 : XXX 2 0 XXXXX Value of EX/MEM : XXXX 2 0 Value of MEM/WB : se the value stored IM Reg sub $2 , $1, $3 execution order (in instructions) DM use the value stored in EX/MEM se the value stored and $12, , $5 or $13, $6, use the value stored in MEM/WB add $14, , 7 sw $15, 100 ($2)
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Forwarding Logic ± Forwarding: input to ALU from any pipe reg.
Background image of page 8
Image of page 9
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 09/24/2009 for the course CSIE CA2009 taught by Professor Yang during the Spring '09 term at National Taiwan University.

Page1 / 45

Lecture_9 - Lecture 9: Pipelining (II) 1. Data Hazards and...

This preview shows document pages 1 - 9. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online