Example 9.1•Design a circuit to compute F = A&B |C&D using NANDs and NORs.SOLUTION: two ANDs and an OR–Figure 9.2(a). •convert to basic CMOS stages–Figure 9.2(b)•bubble push simplifies to three NANDs. –Fig 9.2(c,d)
Ex 9.2•Calculate the minimum delay to compute F = AB + CD using Fig 9.2(d) and 9.3.•Each input can present up to 20 Q of transistor width. •The output must drive a load of 100 Q•Choose transistor sizes to achieve this delay.
•H = 100/20 = 5, B = 1. •NAND gates: G = (4/3) × (4/3) = 16/9, P = 2 + 2 = 4. •AOI22 + inverter: G = (6/3) × 1 = 2, P = 12/3 + 1 = 5.F = GBH =80/9 and 10, respectively. •delays are NF 1/N + P, or 10.0 Y and 11.3 Y, respectively. compound gates not always faster; simple 2-input NAND gates can be fast.
•To compute sizes, determine the best stage efforts, = 3.0 and 3.2,respectively. •in the range of 2.4–6 reasonable •2ndgate: Cin = Cout * g / sqrt(F)•NAND: Cin = 100*(4/3)/3.0 = 44•AOI22: Cin = 100*1/3.2 = 31
Ex 9.3•Size the nMOS transistors in the asymmetric NAND gate for unit pulldown currentconsidering velocity saturation.