chapter4_supplement - Circuit Characterization and Performance Estimation \u2022 CMOS circuit performance is generally determined by equivalent RC

chapter4_supplement - Circuit Characterization and...

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Circuit Characterization and Performance Estimation CMOS circuit performance is generally determined by equivalent RC delays Equivalent resistance of driver circuit (N and P devices) driving a receiver circuit plus wire Load capacitance is comprised of C gate + C wire + C diffusion + C parasitic C gate is the total parallel gate capacitance of receiving circuit(s) C wire is the total wiring capacitance of the interconnect line (metal or poly) C diffusion is the total combined PN junction capacitance of the driving circuit C parasitic is the total equivalent capacitance of the internal integrated wire, etc. Driver resistance consists of some equivalent combination of pull-up and pull- down devices Rp is equivalent resistance of the PFET pull-up device Rn is the equivalent resistance of the NFET pull-down device Metal wire resistance may or may not be important depending on length of net Polysilicon gate resistance may or may not be important depending on length of poly line R. W. Knepper SC571, page 4-1
CMOS Inverter Switching Characteristics Define: Rise time t r = time required for a node to charge from the 10% point to 90% point Fall time t f = time required for a node to discharge from 90% to 10% point Delay time t d = delay from the 50% point on the input to the 50% point on the output Falling delay t df = delay time with output falling Rising delay t dr = delay time with output rising R. W. Knepper SC571, page 4-2
CMOS Inverter Driving a Lumped Capacitance Load CMOS Inverter can be viewed as a single transistor either charging the Cload or discharging the Cload Vin is assumed to switch abruptly If Vin switches high, the NMOS Tx discharges Cload while the PMOS Tx turns OFF If Vin switches low, the PMOS Tx charges Cload while the NMOS Tx turns OFF Cload is comprised of Cgate due to the gate capacitance of receiving circuits Cwire of the interconnect metal Cdiffusion of the inverter output junctions Transient Response: Approximate as a simple RC network where R is given as an equivalent resistance of the NMOS and PMOS devices and C is given as the total lumped Cload capacitance R. W. Knepper SC571, page 4-3
Delay Time Derivation: NMOS Discharging C load Assume Vin switches abruptly from V OL to V OH (V OL = 0 and V OH = V DD for CMOS) We are interested in the delay time for Vout to fall from V OH to the 50% point, i.e. to the value 0.5 x (V OH + V OL ), = ½ V DD for CMOS For Vout between V OH and V OH – V TN , the NMOS is in saturation Integrate C load dv = I dt between t o and t 1’ I DS = ½ k n (V in – V TN ) 2 t 1’ – t o = 2 C load V TN /k n (V OH – V TN ) 2 For Vout between V OH – V TN and V OL , the NMOS is in the linear region Integrate C load dv = I dt between t 1’ and t 1 I DS = k n V DS (V GS – V TN – ½ V DS ) R. W. Knepper SC571, page 4-4
CMOS Inverter Propagation Delay Summary Summing the two delay components from the previous chart, we obtain the expression (at left) for the propagation delay (high-to low) for an NMOS transistor discharging C L For CMOS, V OH = V DD and V OL = 0, so the

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