2OutlineLogical Effort – definition?Delay in a Logic Gate – components?Multistage Logic Networks – watch branches!Number of Stages–Fewer, slower stages vs. more, faster stages–Divide-and-conquer the logical effort neededExample–Classic example is binary-to-hot 1 decoderSummary
4IntroductionChip design choices: –What is the best circuit topology for a function?–How many stages of logic give least delay?–How wide should the transistors be?•Default 2:1 PMOS:NMOS –MicroarchitectureLogical effort method:–Simple rough model of delay–Allows hand calculations–Rapid comparisons of alternatives–Emphasizes symmetries? ? ?
9ExampleDesign a binary address decoder–(binary in, 1 out of N out)Decoder specifications:–16 word register file–32 bit word width (relevant?)–Each bit presents load of 3 unit-sized transistors–True and complementary address inputs A[3:0]–Each input may drive 10 unit-sized transistorsDecide:–How many stages?–Size of each gate?–How fast can it run?A[3:0]A[3:0]1632 bits16 words4:16 DecoderRegister File
12Delay in a Logic GateProcess-independent unitdelay, d = f + pf: effort delay = gh(a.k.a. stage effort)–two componentsg: logical effort–relative ability of gate to deliver current–g1 for any inverter – not just one of unit widthh: electrical effort= Cout/ Cin–output / input capacitance–a.k.a. equivalent fanoutp: parasitic delay from “wasted effort”–Delay when driving no load–Set by internal parasitic capacitanceabsdd 3RC 300 fs in 10 nm process3 ps in 65 nm process60 ps in 0.6 m process
Parasitic delayConstant, independent of transistor sizeDiffusion capacitance at output / 3since diffusion capacitance of inverter = 3Pinvnormalized to 3/3 = 1 N-input NAND or NOR: N*Pinv= N–why?XOR: 4*Pinv= 4N-way MUX: 2*N*Pinv= 4 for 2-way13
14Delay Plotsd= f+ p= gh+ pWhat about NOR2?
15Computing Logical EffortDEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.Measure from delay vs. fanout plotsOr estimate by counting transistor widthsAYABYABY1211222244Cin= 3g = 3/3Cin= 4g = 4/3Cin= 5g = 5/3
Logical EffortDefinition 4.1 The logical effort of a logic gate is defined as the number of times worse it is at delivering output current than would be an inverter with identical input capacitance. 16
Per Input / BundleLogical effort per input: effectiveness of a single input in controlling output current.