lect6-logicaleffort_jae - Lecture 7 Logical Effort W&H Ch 4 1 Outline Logical Effort \u2013 definition Delay in a Logic Gate \u2013 components Multistage

# lect6-logicaleffort_jae - Lecture 7 Logical Effort W&H...

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Lecture 7: Logical Effort W&H Ch 4 1
2 Outline Logical Effort – definition? Delay in a Logic Gate – components? Multistage Logic Networks – watch branches! Number of Stages Fewer, slower stages vs. more, faster stages Divide-and-conquer the logical effort needed Example Classic example is binary-to-hot 1 decoder Summary
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4 Introduction Chip design choices: What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be? Default 2:1 PMOS:NMOS Microarchitecture Logical effort method: Simple rough model of delay Allows hand calculations Rapid comparisons of alternatives Emphasizes symmetries ? ? ?
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9 Example Design a binary address decoder ( binary in, 1 out of N out ) Decoder specifications: 16 word register file 32 bit word width (relevant?) Each bit presents load of 3 unit-sized transistors True and complementary address inputs A[3:0] Each input may drive 10 unit-sized transistors Decide: How many stages? Size of each gate? How fast can it run? A[3:0] A[3:0] 16 32 bits 16 words 4:16 Decoder Register File
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Current Amplification 11
12 Delay in a Logic Gate Process-independent unit delay, d = f + p f : effort delay = g h (a.k.a. stage effort) two components g : logical effort relative ability of gate to deliver current g 1 for any inverter – not just one of unit width h : electrical effort = C out / C in output / input capacitance a.k.a. equivalent fanout p : parasitic delay from “wasted effort” Delay when driving no load Set by internal parasitic capacitance abs d d   3RC 300 fs in 10 nm process 3 ps in 65 nm process 60 ps in 0.6 m process
Parasitic delay Constant, independent of transistor size Diffusion capacitance at output / 3 since diffusion capacitance of inverter = 3 P inv normalized to 3/3 = 1 N-input NAND or NOR: N*P inv = N why? XOR: 4*P inv = 4 N-way MUX: 2*N*P inv = 4 for 2-way 13
14 Delay Plots d = f + p = gh + p What about NOR2?
15 Computing Logical Effort DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current . Measure from delay vs. fanout plots Or estimate by counting transistor widths A Y A B Y A B Y 1 2 1 1 2 2 2 2 4 4 C in = 3 g = 3/3 C in = 4 g = 4/3 C in = 5 g = 5/3
Logical Effort Definition 4.1 The logical effort of a logic gate is defined as the number of times worse it is at delivering output current than would be an inverter with identical input capacitance. 16
Per Input / Bundle Logical effort per input: effectiveness of a single input in controlling output current.
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