See discussions, stats, and author profiles for this publication at: Pulsed-latch circuits to push the envelope of ASIC designArticle· November 2010DOI: 10.1109/SOCDC.2010.5682949CITATIONS3READS1,0902 authors:Seungwhun PaikSynopsys24PUBLICATIONS171CITATIONSSEE PROFILEYoungsoo ShinKorea Advanced Institute of Science and Technology151PUBLICATIONS1,663CITATIONSSEE PROFILEAll content following this page was uploaded by Seungwhun Paik on 13 March 2015.The user has requested enhancement of the downloaded file.
Pulsed-Latch Circuits to Push the Envelope ofASIC DesignSeungwhun Paik and Youngsoo ShinDepartment of Electrical Engineering, KAISTDaejeon 305-701, KoreaAbstract—The use of the slow and power-consuming flip-flopsis one of the factors that cause a large gap between custom andASIC designs. A pulsed-latch, which is a latch driven by a briefpulse clock, inherits the advantage of latch while allowing us touse a simple timing model similar to that of flip-flop. As a result,it offers the opportunity of higher performance and lower powerconsumption within the conventional ASIC design environment.We address challenges and problems specific to pulsed-latchASIC, and review potential solutions. Some quantitative resultsare provided to assess the effectiveness of pulsed-latch circuits.I. INTRODUCTIONMost ASIC designs use an edge-triggered flip-flop as asequencing element. This is because of simple timing modelit offers; each combinational block between two flip-flopscan be considered isolated. This enables timing analysis athigher design abstraction, which then supports timing-drivensynthesis. An example is technology mapping, which receivesBoolean expressions and determines corresponding connectionof logic gates. The mapping can be performed while assumingthat the computation of each expression is finished within aclock period.However, flip-flops take an appreciable portion of clock pe-riod, total power consumption, and circuit area. The proportionof sequencing overhead of flip-flop (i.e. sum of clock-to-Qdelay and setup time) in a clock period increases as clockfrequency increases due to ever-increasing demand on highperformance. The sequencing overhead of a typical flip-flop is6 FO4 delay ; this is 13% of 46 FO4 delay of clock period,and 17% and 21% when clock period becomes 35 and 29FO4 delay, respectively . Clock distribution network oftencontributes more than half of total power consumption; almosthalf of the clocking power is consumed by flip-flops .Since flip-flops are commonly designed by cascading twotransparent latches, their sequencing overhead is about twicethat of latches. This explains why latches are frequently used inhigh-performance custom designs. Latches also have smallerclock load due to smaller number of clocked transistors. How-ever, time borrowing, along with requirement of two-phasenon-overlapping clocking, complicates the timing analysis oflatches, which makes them difficult to use in ASIC designs.