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See discussions, stats, and author profiles for this publication at: Pulsed-latch circuits to push the envelope of ASIC design Article · November 2010 DOI: 10.1109/SOCDC.2010.5682949 CITATIONS 3 READS 1,090 2 authors: Seungwhun Paik Synopsys 24 PUBLICATIONS 171 CITATIONS SEE PROFILE Youngsoo Shin Korea Advanced Institute of Science and Technology 151 PUBLICATIONS 1,663 CITATIONS SEE PROFILE All content following this page was uploaded by Seungwhun Paik on 13 March 2015. The user has requested enhancement of the downloaded file.
Pulsed-Latch Circuits to Push the Envelope of ASIC Design Seungwhun Paik and Youngsoo Shin Department of Electrical Engineering, KAIST Daejeon 305-701, Korea Abstract —The use of the slow and power-consuming flip-flops is one of the factors that cause a large gap between custom and ASIC designs. A pulsed-latch, which is a latch driven by a brief pulse clock, inherits the advantage of latch while allowing us to use a simple timing model similar to that of flip-flop. As a result, it offers the opportunity of higher performance and lower power consumption within the conventional ASIC design environment. We address challenges and problems specific to pulsed-latch ASIC, and review potential solutions. Some quantitative results are provided to assess the effectiveness of pulsed-latch circuits. I. I NTRODUCTION Most ASIC designs use an edge-triggered flip-flop as a sequencing element. This is because of simple timing model it offers; each combinational block between two flip-flops can be considered isolated. This enables timing analysis at higher design abstraction, which then supports timing-driven synthesis. An example is technology mapping, which receives Boolean expressions and determines corresponding connection of logic gates. The mapping can be performed while assuming that the computation of each expression is finished within a clock period. However, flip-flops take an appreciable portion of clock pe- riod, total power consumption, and circuit area. The proportion of sequencing overhead of flip-flop (i.e. sum of clock-to-Q delay and setup time) in a clock period increases as clock frequency increases due to ever-increasing demand on high performance. The sequencing overhead of a typical flip-flop is 6 FO4 delay [1]; this is 13% of 46 FO4 delay of clock period, and 17% and 21% when clock period becomes 35 and 29 FO4 delay, respectively [2]. Clock distribution network often contributes more than half of total power consumption; almost half of the clocking power is consumed by flip-flops [3]. Since flip-flops are commonly designed by cascading two transparent latches, their sequencing overhead is about twice that of latches. This explains why latches are frequently used in high-performance custom designs. Latches also have smaller clock load due to smaller number of clocked transistors. How- ever, time borrowing, along with requirement of two-phase non-overlapping clocking, complicates the timing analysis of latches, which makes them difficult to use in ASIC designs.

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