Pulsed-Latch Circuits:A New Dimensionin ASIC DesignYoungsoo ShinKAISTSeungwhun PaikSynopsysĸACONVENTIONALASICdesign mainly uses anedge-triggered flip-flop as a sequencing element be-cause of the simplicity of this flip-flop’s timingmodel. Specifically, the amount of time available toa combinational block that lies between two flip-flops is fixed. This constrains timing uncertaintieswithin each combinational block, which is importantfor design steps at higher abstraction levels such aslogic synthesis when implementation details are un-known. However, an appreciable portion of theclock period, total power consumption, and circuitarea are attributed to flip-flops. A typical flip-flophas 6 FO4 (fanout-of-4) delays (sum of the clock-to-Q delay and the setup time).1This is 13% of a 46-FO4-delay clock period, and 17% and 21% when theclock period becomes 35 and 29 FO4 delays, respec-tively,2due to the requirement to increase the clockfrequency. The clock distribution, including flip-flops, often contributes more than half of the totalpower consumption.High-performance custom designs often use alevel-sensitive latch as a sequencing element. Its tim-ing overhead ranges from 2 to 4 FO4 delays,1whichis far smaller than that of a flip-flop. Such designsare somewhat immune to clock skew and jitter,owing to latch transparency. However, the timingmodel is more complicated, which, along with thelimited support of CAD tools, makes using latches inASIC designs difficult. In addition, datamust be held for a longer period oftime, increasing the likely number ofhold time violations.Apulsed latchis a latch that is drivenby a brief clock pulse. The amount oftimeavailabletoacombinationalblock is still variable, but the amountof variation is significantly less than in latch circuits.The scope for hold time violations is also reduced.This makes a pulsed latch an ideal sequencing ele-ment for high-performance and low-power ASICdesigns, as well as for traditional high-performancemicroprocessor designs.3-9Given the similarity of the timing model, a pulsedlatch can be approximated by a faster flip-flop. Thisenables a simple migration of a flip-flop circuit to apulsed-latch version by substituting all (or some) ofthe sequencing elements,10thus saving both theclock period and power consumption. We have per-formed experiments using some test circuits to exam-ine the savings quantitatively. Additional support ofthe design methodology and tools is necessary for acomplete environment of ASIC design based onpulsed latches.In this article, we discuss this additional sup-port forĸthe physical design, including insertion of pulsegenerators and customized placement algorithms;ĸtiming analysis and optimization, including bufferinsertion to resolve hold time violations, time bor-rowing via different pulse widths, and mixed timeborrowing and sequential optimization; andĸlow-power design, including clock gating in pulsed-latch circuits.