pulsed_laches.pdf - [3B2-9 mdt2011060050.3d 14:56 Page 50 Pulsed-Latch Circuits Pulsed-Latch Circuits A New Dimension in ASIC Design Youngsoo Shin KAIST

pulsed_laches.pdf - [3B2-9 mdt2011060050.3d 14:56 Page 50...

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Pulsed-Latch Circuits: A New Dimension in ASIC Design Youngsoo Shin KAIST Seungwhun Paik Synopsys ĸ A CONVENTIONAL ASIC design mainly uses an edge-triggered flip-flop as a sequencing element be- cause of the simplicity of this flip-flop’s timing model. Specifically, the amount of time available to a combinational block that lies between two flip- flops is fixed. This constrains timing uncertainties within each combinational block, which is important for design steps at higher abstraction levels such as logic synthesis when implementation details are un- known. However, an appreciable portion of the clock period, total power consumption, and circuit area are attributed to flip-flops. A typical flip-flop has 6 FO4 (fanout-of-4) delays (sum of the clock-to- Q delay and the setup time). 1 This is 13% of a 46- FO4-delay clock period, and 17% and 21% when the clock period becomes 35 and 29 FO4 delays, respec- tively, 2 due to the requirement to increase the clock frequency. The clock distribution, including flip- flops, often contributes more than half of the total power consumption. High-performance custom designs often use a level-sensitive latch as a sequencing element. Its tim- ing overhead ranges from 2 to 4 FO4 delays, 1 which is far smaller than that of a flip-flop. Such designs are somewhat immune to clock skew and jitter, owing to latch transparency. However, the timing model is more complicated, which, along with the limited support of CAD tools, makes using latches in ASIC designs difficult. In addition, data must be held for a longer period of time, increasing the likely number of hold time violations. A pulsed latch is a latch that is driven by a brief clock pulse. The amount of time available to a combinational block is still variable, but the amount of variation is significantly less than in latch circuits. The scope for hold time violations is also reduced. This makes a pulsed latch an ideal sequencing ele- ment for high-performance and low-power ASIC designs, as well as for traditional high-performance microprocessor designs. 3-9 Given the similarity of the timing model, a pulsed latch can be approximated by a faster flip-flop. This enables a simple migration of a flip-flop circuit to a pulsed-latch version by substituting all (or some) of the sequencing elements, 10 thus saving both the clock period and power consumption. We have per- formed experiments using some test circuits to exam- ine the savings quantitatively. Additional support of the design methodology and tools is necessary for a complete environment of ASIC design based on pulsed latches. In this article, we discuss this additional sup- port for ĸ the physical design, including insertion of pulse generators and customized placement algorithms; ĸ timing analysis and optimization, including buffer insertion to resolve hold time violations, time bor- rowing via different pulse widths, and mixed time borrowing and sequential optimization; and ĸ low-power design, including clock gating in pulsed- latch circuits.

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