Basics of latch timing.doc - Basics of latch timing A latch is a digital logic circuit that can sample a 1-bit digital value and hold it depending upon

Basics of latch timing.doc - Basics of latch timing A latch...

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Basics of latch timing A latch is a digital logic circuit that can sample a 1-bit digital value and hold it depending upon the state of an enable signal. Based upon the state of enable, latches are categorized into positive level-sensitive and negative level-sensitive latches. Positive level-sensitive latch : A positive level-sensitive latch follows the input data signal when enable is '1' and keeps its output when the data when it is '0'. Figure 1 below shows the symbol and the timing waveforms for a latch. As can be seen, whenever enable is '1', out follows the data input. And when enable in '0', out remains the same. Figure 1(a): Positive level- Figure 1(b): Timing waveform for a positive level- sensitive latch sensitive latch Negative level-sensitive latch : A negative level-sensitive latch follows the input data when enable is '0' and keeps its output when input is '1'. Figure 2(a): Negative level- Figure 2(b): Timing waveform for a negative level- sensitive latch sensitive latch Latch timing arcs : Data can propagate to the output of the latch in two ways as discussed below: Out changes with Data : This happens when enable is in its asserted state (for example, for a positive level latch). When this happens, Out follows Data as there is a direct path between Data and Out when Enable is '1'. This scenario is

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