chapter01 - Chapter 1 Review of Logic Chapter 1 Review of...

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1 Michigan State University, East Lansing, MI, U.S.A. ECE 411: Electronic Design Automation URL: http:// angel.msu.edu angel.msu.edu Adapted from the publisher’s lecture slides PROF ROF . NIHAR IHAR R . . MAHAPATRA AHAPATRA E-mail: mail: [email protected] Chapter 1: Review of Logic Design Fundamentals Design Fundamentals 2 Outline Outline ) Course information and administrivia ) Course overview: ¾ Ch. 1: Review of logic design fundamentals ¾ Ch. 2: Introduction to VHDL ¾ Ch. 3: Introduction to programmable logic devices ¾ Ch. 4: Design examples ¾ Ch. 5: State machine (SM) charts and microprogramming ¾ Ch. 6: Designing with field programmable gate arrays (FPGAs) ¾ Ch. 8: Additional topics in VHDL ¾ Ch. 10: Hardware testing and design for testability
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2 3 Outline Outline ) Chapter 1: We review in turn the fundamentals of the two basic types of logic design blocks: ¾ Combinational logic: Has no memory, so present output depends only upon present input ¾ Sequential logic: Present output depends not only present input, but also on past sequence of inputs 4 Basic Gates Basic Gates Basic Gates Fig. 1-1
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3 5 Minterm Expansion and m -Notation (or Decimal Notation) Minterm Minterm Expansion and m -Notation Notation (or Decimal (or Decimal Notation) Notation) Fig. 1-2 ) Minterm expansion or sum of products (SOP) comprises minterms corresponding to “1”s in the truth table 6 Maxterm Expansion and M -Notation (or Decimal Notation) Maxterm Maxterm Expansion and Expansion and M -Notation Notation (or Decimal (or Decimal Notation) Notation) Fig. 1-2 ) Maxterm expansion or products of sums (POS) comprises maxterms corresponding to “0”s in the truth table
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4 7 Boolean Logic Expression Simplification Boolean Logic Expression Simplification Boolean Logic Expression Simplification ) Motivations: ¾ To optimize a circuit to use a smaller number of gates ¾ To map circuits to particular target devices where only certain types of logic (e.g., NAND only or NOR only) are available ) Methods: ¾ Using Boolean algebra laws and theorems ¾ Using (graphical) Karnaugh maps ¾ Using (tabular) Quine-McCluskey method – can handle any number of Boolean variables and suitable for automation (will not study it) 8 Laws and Theorems of Boolean Algebra Laws and Theorems of Boolean Algebra Laws and Theorems of Boolean Algebra Listed in Dual Pairs
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5 9 Logic Simplification Examples Logic Simplification Examples Logic Simplification Examples 10 Karnaugh Maps for Logic Simplification Karnaugh Maps for Logic Simplification Karnaugh Maps for Logic Simplification ) K-maps useful to simplify logic functions of 3-5 variables, with each square representing a possible minterm ¾ 1 minterm present; 0 minterm absent; X don’t care because: Ö Corresponding input combination can never occur or Ö Input combination can occur, but corresponding circuit output unspecified ) Variable values ordered so that adjacent squares differ in only one variable and can be combined ( xy + xy’ = x ) to eliminate a variable
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6 11 Obtaining a Minimum SOP from a K-map Obtaining a Minimum SOP from a K
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This note was uploaded on 09/27/2009 for the course ECE 411 taught by Professor Staff during the Fall '08 term at Michigan State University.

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chapter01 - Chapter 1 Review of Logic Chapter 1 Review of...

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