Lecture-02

Lecture-02 - EEE 333: VHDL, L-02 Fall 2009, ASU David R....

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Unformatted text preview: EEE 333: VHDL, L-02 Fall 2009, ASU David R. Allee, allee@asu.edu , GWC 234 CMOS Technology and IC Design EEE 333, ASU, D.Allee Lecture 02- 2 - Highlight MOSFET basics The structure and operation First-order model: a switch + a resistor CMOS logic: inverter Logic gate construction Static and dynamic behavior Delay model Interconnect and package Reading: Chapter 2 in Wolfs book Further reading: Chapter 3 and 5 in Rabaeys book EEE 333, ASU, D.Allee Lecture 02- 3 - Highlight MOSFET basics The structure and operation First-order model: a switch + a resistor CMOS logic: inverter Logic gate construction Static and dynamic behavior Delay model Interconnect and package Reading: Chapter 2 in Wolfs book Further reading: Chapter 3 and 5 in Rabaeys book EEE 333, ASU, D.Allee Lecture 02- 4 - 3D Perspective of a MOSFET Polysilicon/Metal Gate Aluminum/Copper MOSFET: Metal-Oxide-Semiconductor Field Effect Transistor EEE 333, ASU, D.Allee Lecture 02- 5 - Technology Evolution 50nm 2002 (90nm node) G a t e S o u r c e D r a i n 15nm 2015 ? 1947 ???? New materials and structures to keep the scaling Improve carrier mobility (e.g., SiGe channel) Reduce gate/S/D resistance (e.g., metal-gate, Ge for S/D) Suppress gate and channel leakage (e.g., high-k insulator) EEE 333, ASU, D.Allee Lecture 02- 6 - Critical Dimensions (90nm) V th Control: ~100 dopants Channel Length 12 (~5 atoms) EEE 333, ASU, D.AlleeEEE 333, ASU, D....
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Lecture-02 - EEE 333: VHDL, L-02 Fall 2009, ASU David R....

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