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Unformatted text preview: 1 10 01 00, 01 00, 10 c. Fig. 2 shows a Set-Reset latch. Instead of a clock signal, the signals of set (S) and reset (R) control the value of Q. Note that S=R=1 is an illegal set of input, since Q and Q are not complementary under that condition. What is the logic function to derive Q_next from S, R, and Q? Q R S next Q ⋅ + = _ d. Define the state of an S-R latch as the value of Q, and the control signal as the legal value of SR. Draw the state diagram of a S-R latch....
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- Fall '09
- Logic gate, s-r latch, R. Allee Homework