{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

HW 1 - solution

# HW 1 - solution - 1 10 01 00 01 00 10 c Fig 2 shows a...

This preview shows pages 1–2. Sign up to view the full content.

A B C A 0 0 0 011111 0 0 0 1 101100 1 0 1 0 101010 1 0 1 1 101000 1 1 0 0 100110 1 1 0 1 100100 1 1 1 0 100010 1 1 1 1 100000 1 1 0 1 1 0 0 EEE 333, ASU Fall 2009, David R. Allee Homework #1 1. Boolean Logic 2. CMOS Implementation (a) ( 29 B B B A + = B (it is just a wire connecting the input and output. No gate needed) (b) C B A A + = C A C A = + . Three NAND gates are needed. (c) A C B A + + = A, no gate needed. 3. Sequential Logic a. A toggle flip-flop has the input T as an enable signal. This FF changes its state at the clock edge as shown in Fig. 1, where Q_next is the value of Q at the next cycle. What is the logic function to derive Q_next from T and Q? Q T Q T next Q + = _ b. Define the state of this T-FF as the value of Q. Draw the state diagram of a T-FF.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 1 10 01 00, 01 00, 10 c. Fig. 2 shows a Set-Reset latch. Instead of a clock signal, the signals of set (S) and reset (R) control the value of Q. Note that S=R=1 is an illegal set of input, since Q and Q are not complementary under that condition. What is the logic function to derive Q_next from S, R, and Q? Q R S next Q ⋅ + = _ d. Define the state of an S-R latch as the value of Q, and the control signal as the legal value of SR. Draw the state diagram of a S-R latch....
View Full Document

{[ snackBarMessage ]}

### Page1 / 2

HW 1 - solution - 1 10 01 00 01 00 10 c Fig 2 shows a...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online