Lecture-01

Lecture-01 - EEE 333: VHDL, L-01 Introduction Fall 2009,...

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EEE 333: VHDL, L-01 Fall 2009, ASU David R. Allee, allee@asu.edu , GWC 234 Introduction
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EEE 333, ASU, D. Allee Lecture 01 - 2 - Highlight Course orientation Objective, textbook, assignments, and grading policy Acknowledgement: course materials from Professors Clark and Cao , ASU VLSI design methodology History, today, and tomorrow Synthesis (top-down) vs. Custom (bottom-up) Handout: Syllabus and Tentative Schedule
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EEE 333, ASU, D. Allee Lecture 01 - 3 - Basic Information Instructor: David R. Allee, GWC 234 Office hour: T/Th, 3pm – 4pm ; E-mail: allee@asu.edu TA: Siddesh Mhambre smhambre@asu.edu Satendra Maurya satendra.maurya@asu.edu Divya Pratap divya.pratap@asu.edu Textbook: The Designer’s Guide to VHDL , by Peter J. Ashenden, 2 nd Ed. FPGA-Based System Design , by Wayne Wolf Other references: HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog , by Douglas J. Smith Digital Integrated Circuits: A Design Perspective , by Jan M. Rabaey, et al. ( http://bwrc.eecs.berkeley.edu/IcBook/ ) Lab at GWC 273, with TA available Lectures etc. are available at http://my.asu.edu
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EEE 333, ASU, D. Allee Lecture 01 - 4 - What will You Learn VHDL language for contemporary VLSI design, with practical applications to FPGA systems Content: CMOS digital synthesis, VHDL coding and modeling, combinational and sequential logic, architecture, and FPGA hardware Pre-requisite
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Lecture-01 - EEE 333: VHDL, L-01 Introduction Fall 2009,...

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