Lecture-04

Lecture-04 - EEE 333: VHDL, L-04 Sequential Circuit Fall...

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EEE 333: VHDL, L-04 Fall 2009, ASU David R. Allee, [email protected] , GWC 234 Sequential Circuit
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EEE 333, ASU, D.Allee Lecture 04 - 2 - Highlight Sequential system Sequential logic design Elements: Latch and Flip-Flop Timing issues Reading: Chapter 2 in Wolf’s book Further reading: Chapter 7.1 and 7.2 in Rabaey’s book Assignment at myasu: HW 1
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EEE 333, ASU, D.Allee Lecture 04 - 3 - Highlight Sequential system Sequential logic design Elements: Latch and Flip-Flop Timing issues Reading: Chapter 2 in Wolf’s book Further reading: Chapter 7.1 and 7.2 in Rabaey’s book Assignment at myasu: HW 1
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EEE 333, ASU, D.Allee Lecture 04 - 4 - Combinational Logic Units Arithmetic Logic Unit (ALU) is the core of a microprocessor Is that enough to construct a system? FA FA FA FA A 0 B 0 S 0 A 1 B 1 S 1 A 2 B 2 S 2 A 3 B 3 S 3 C i ,0 C o ,0 ( = C i ,1 ) C o ,1 C o ,2 Cout a Sum Cin b
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Lecture 04 - 5 - A Digital Processor Control: finite-state-machine, counters, etc. Datapath: adder, multiplier, shifter, etc. Memory: registers, RAM, ROM, etc. Others: I/O, switches, etc.
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This note was uploaded on 09/28/2009 for the course EEE 352/333 taught by Professor Allee during the Fall '09 term at ASU.

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Lecture-04 - EEE 333: VHDL, L-04 Sequential Circuit Fall...

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