Lecture-05

Lecture-05 - EEE 333: VHDL, L-05 VHDL Basics Fall 2009, ASU...

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EEE 333: VHDL, L-05 Fall 2009, ASU David R. Allee, allee@asu.edu , GWC 234 VHDL Basics
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EEE 333, ASU, D.Allee Lecture 05 - 2 - Highlight Overview of VHDL VHDL 101 Entity and Architecture Behavioral and Structural elements Reading: Chapter 1 in Ashenden’s book A good VHDL tutorial is posted at myasu Announcement: Lab information
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EEE 333, ASU, D.Allee Lecture 05 - 3 - Announcement: Lab Lab: GWC 273 EECAD servers with your ASURite account Sign in at the front desk TA: TA lab hours: Time Mon Tue Wed Thu Fri 10:30 12:30 2:30 4:30 6:30 8:30 General lab hours:
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EEE 333, ASU, D.Allee Lecture 05 - 4 - Warm up Lab warm-up Go to the lab and log on to a EECAD server Access the tutorial from /usr/local/modeltech/docs/pdf Work through the tutorial, se_tutor.pdf , Lesson1, 2, and 3. If you have any questions Contact TA for lab questions Discuss with your classmates Check MyASU Come to my office hours
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EEE 333, ASU, D.Allee Lecture 05 - 5 - Highlight Overview of VHDL VHDL 101 Entity and Architecture Behavioral and Structural elements Reading: Chapter 1 in Ashenden’s book A good VHDL tutorial is posted at myasu Announcement: Lab information
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EEE 333, ASU, D.Allee Lecture 05 - 6 - A Digital Processor Control: finite-state-machine, counters, etc. Datapath: adder, multiplier, shifter, etc. Memory: registers, RAM, ROM, etc. Others: I/O, switches, etc. MEMORY DATAPATH CONTROL INPUT-OUTPUT
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EEE 333, ASU, D.Allee Lecture 05 - 7 - Design Methodology Functional Structural Geometric Algorithm (behavioral) Register-Transfer Language Boolean Equation Differential Equation Processor-Memory Switch Register-Transfer Gate Transistor Polygons Sticks Standard Cells Floor Plan
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EEE 333, ASU, D.Allee Lecture 05 - 8 - Hardware Description Language A high-level computer language can model, represent and simulate digital design Similar as a programming language (e.g., C) Describe the hardware Semantics for signal value and time Stimulate the circuit and check its response Goals with HDL Reliable design process, with minimum cost and time Technology independent and avoid design errors
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EEE 333, ASU, D.Allee
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Lecture-05 - EEE 333: VHDL, L-05 VHDL Basics Fall 2009, ASU...

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