Lecture-07

Lecture-07 - EEE 333: VHDL, L-07 VHDL Modeling Fall 2009,...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
EEE 333: VHDL, L-07 Fall 2009, ASU David R. Allee, allee@asu.edu , GWC 234 VHDL Modeling
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EEE 333, ASU, D.Allee Lecture 07 - 2 - Highlight Data objects and types Signals, variables, and constants Scalar types Composite type Modeling of combinational logic Modeling architecture Behavioral descriptions Process statement Reading: Chapter 4, 5 in Ashenden’s book Assignment at myasu: HW 2
Background image of page 2
EEE 333, ASU, D.Allee Lecture 07 - 3 - Highlight Data objects and types Signals, variables, and constants Scalar types Composite type Modeling of combinational logic Modeling architecture Behavioral descriptions Process statement Reading: Chapter 4, 5 in Ashenden’s book Assignment at myasu: HW 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EEE 333, ASU, D.Allee Lecture 07 - 4 - Composite Types Scalar types consist of single, indivisible values Example: integer , physical, enumerated, std_logic , etc. Composite types consist of data elements in the form of an array or an record We can manipulate the entire object or each individual element Array: a collection of values that are the same type Each values position is indexed by a scalar value type word is array (0 to 31) of bit; type word is array (31 downto 0) of bit; The indexes don’t have to be numeric, they can be enumerated type controller_state is (initial, idle, active, error); type state_counts is array (idle to error) of natural; The index type has to be clear from the context Otherwise, it needs to be made clear explicitly type state_counts is array (controller state range idle to error) of natural;
Background image of page 4
EEE 333, ASU, D.Allee Lecture 07 - 5 - Arrays You can first specify a subtype for the index subtype ram_address is integer range 63 downto 0; type ram_array is array (ram_address) of real; After defining the array type, you can define objects of that type variable buffer_register, data_register: word; variable counters: state_counts; variable coefficients: ram_array; The array is used as arrays in other programming languages coeff(0) := 0.0; counters(active) := counters(active) + 1; As a composite object, an array can be copied en-masse data_register := buffer_register;
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EEE 333, ASU, D.Allee Lecture 07 - 6 - Example: RAM RAM is an array of memory cells begin for index in ram_address loop coeff(index) := 0.0; end loop; loop wait on rd, wr, addr, dataIn; if rd = ‘1’ then dataOut <= coeff(addr); end if ; if wr = ‘1’
Background image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 20

Lecture-07 - EEE 333: VHDL, L-07 VHDL Modeling Fall 2009,...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online