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Logic_Probe_Guide - APPENDIX"C THE LPvl LOGIC PROBE...

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Unformatted text preview: APPENDIX "C THE LPvl LOGIC PROBE Cl .0 introduction The LPJ logic probe is used to detect and display logic levels, pulses and voltage transients in mixed and single family logic systems. It will detect out—of—tolerance logic signals, open-circuit nodes, and transient signals greater then 50 us. See Figure Cl . C2.0 Technical Description The probe tip of the LP-l is connected to a dual threshold window comparator and a bipolar edge detector. A windOw comparator bias network establishes the LOGIC "l" and LOGIC "0" threshold levels. The levels are fixed in the DTIflTL mode at 2.25 volts and 0.8 volts. In the CMOS/IITL mode, the thresholds are determined by the applied Vcc voltage with LOGIC "l " > 70% ofVcc and LOGIC "0" < 30% Vcc. ‘ The bipolar edge detector reSponds to both positive and negative transitions and drives a pulse stretcher circuit. The pulse stretcher converts level transitions as well as narrow pulses to 1/3 of a second pulses that drive one of the three readout LEDs. In the memory mode the output ofthe edge detector is fed to a latching flip—flop. ’ C3.0 Instructions for Use Connect the logic probe's leads to the Circuit's power supply. The logic probe is protected againsr over-voltage and reverse voltage on its power leads. Connect the black banana plug lead to the common H and the red banana plug lead to plus (+) Vcc. In order to minimize me possibility of power surnply spikes. or other spurious signals, from affecting the operation of the probe, connect the power leads as close as possible to the node to be tested. NOTE: THE COMMON OR GROUND POINT FROM THE EXTERNAL SUPPLY MUST BE CONNECTED TO THE CIRCUIT GROUND LINE OF THE CIRCUIT UNDER TEST. Set the logic family switch to DTL/TTI. or CMOS/HTL and the MEMORY/PULSE switch to the PULSE position. Setting the Logic Family switch to the DTL/TTL position programs the logic probe window comparator for LOGIC "l " of2.25 volts or greater (up to Vcc) and a LOGIC "0" of0.8 volts or less. In the CMOS position, LOGIC "l" and LOGIC "0" levels are determined by the applied Vcc. LOGlC "l " > 70% Vcc and LOGIC "O" < 30% VCC. ECE 33] Laboratory Manual Touch the probe tip to the circuit node to be analyzed. The three diSplay LEDS on the probe , body wili instantly provide a reading of the signal activity at the node. (3.1 Memory/Pulse SWitch The memory mode of the logic probe is used to detect, store and display low rep rate or single shot pulses and some transient events. Pulse positiOn: Each time the input signal changes state \fli. e. \fR, Logic 1 -> 0 or Logic 0 -> 1 the PULSE LED is activated for 0.3 seconds. When observing low frequency, low duty cycle signals, the PULSE LED provides an immediate indication of the pulse activity at the node under test. By observing the H] and LO LEDs, the phase of the pulse train can immediately be determined, \fli e. \iR, if the HI LED is on, the signal IS normally high and pulsing low and \flvisa versa\tR. High frequency signals cause the PULSE LED to flash at a 3H2 rate Memory position: The logic probe contains a pulse memory flip-flop that latches level lTaflSiliQns 01’ P111555 as narrow as 50115. The memory is activated by either positive or negative level transition. To set the probe for latching an event, touch the probe tip to the node under 1851; move 1116 MEM/PULSE switch to the MEM position. The next event that occurs at the node will activate the PULSE LED and latch To reset and rear-m the latch, move the MEM/PULSE switch to the PULSE position and then return it to the MEM position. NOTE: WHEN ARMING THE MEMORY THE PROBE TIP MUST BE TN CONTACT WlTH THE NODE UNDER TESTJF THE MEMORY lS ARMED WITH THE TIP FLOATING (UNCONNECTED) THE WMORY \NILL BE ACTIVATED WHEN THE TIP IS BROUGHT IN CONTACT WITH THE TEST POINT YIELDING A FALSE READOUT. Figure CI. The LP—l logic probe. ECE 33l Laboratory Manual m. m. w m L m m g E P. 532.12” finite?“ Pn- . — ...
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Logic_Probe_Guide - APPENDIX"C THE LPvl LOGIC PROBE...

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