ECE 331 Spring 2009 p. 1 Lab 5: Synchronous State Machine Design Summary: Design and implement synchronous state machine circuits and test them using a logic analyzer. Learning Objectives: •Experience state machine design procedure •Experience using a PC-based logic analyzer Resources and Supplies: •Logic Analyzer Tutorial*•Protoboard Guide* •IC Data Sheet* •Logic Probe Guide* •Wire cutters •IC’s kit •331 protoboard •Power supply •Logic probe •Safety glasses (required!) All documents* are available on the class websiteImportant Reminders: •Bring your SRB to lab. •Pre-lab assignments must be completed beforecoming to the lab. Background: Synchronous state sequencer: Please see the State Machine Introductionclass notes for a more thorough description of state machines and their implementation using flip flops. Figure 1 illustrates the states for a 2 bit sequencer. Synchronous state machines are typically implemented using flip-flop circuits. In this lab you will be asked to design and implement a state machine using the DM7476 J-K FF IC that can be reset to the initial 0,0 state when the momentary switch button on your SRB is pressed. This is called an asynchronous reset because it acts regardless of the clock state. You can use the PR and/or CLR inputs of the DM7476 and simple logic to realize the reset function. Figure 1. Illustration of states in a 2-bit synchronous state sequencer. 10 11
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