Lab_3 - ECE 331 Spring 2009 Lab 3 Latches and Registers...

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ECE 331 Spring 2009 Lab 3: Latches and Registers Summary: Review the operation of latches and flip-flops to lay a foundation for understanding the use of registers found within microprocessor architectures. Learning Objectives: Observe the basic operation of flip-flops and latches Experience the use of the clock and pulse generation functions on the SRB Resources and Supplies: SRB Guide* Protoboard Guide* IC Data Sheet* Wiring Diagram Template* IC’s kit Wire cutters 331 protoboard Power supply Logic probe Safety glasses All documents* are available on the internet or class website Important Reminders: Bring your SRB to lab. Each student should always bring his/her own SRB. Pre-lab assignments must be completed before coming to the lab. Background: S’R’ latch: The circuit shown in Figure 1 is an S’R’ latch. The inputs are generally designated S and R for "Set" and "Reset", respectively. Unlike an SR latch, the hold, state of the S’R’ latch occurs at (1,1). Also, it operates with active low signals. That is, the latch is set (Q=1) when S’ Æ 0 and reset (Q=0) when R’ Æ 0 (assume a starting state of 1,1). (0,0) is a restricted state; in this state Q and Q’ outputs would actually hold the same value. See for more information. You can test the operation of the NAND S’R’ latch at . Figure 1. S’R’ Latch, schematic and truth table S’ R’ Q 0 0 restricted 0 1 1 1 0 0 1 1 hold p. 1
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ECE 331 Spring 2009 JK flip-flop: A JK latch is an expansion of the SR latch where the restricted state takes on the function of toggle , inverting the output from its previous value. The JK latch can be implemented with four 2-input NAND gates. Other gate configurations will also work. The characteristic equation of the JK latch is prev prev next Q K Q J Q + = . A disadvantage of the JK latch is that the output can change any time J and/or K change. Often it would be preferable if the output changed only when a control signal enabled it to change. This control signal can have many names including enable, gate, or mask and results in a level-triggered JK flip-flop that operates as a JK latch when the control signal is at logic high (or low, depending on the circuit design). In some situations this control signal might be connected to a clock. A level-triggered JK latch with a clock enable signal is shown in Figure 2 along with a table of its characteristic operation when the clock signal is high. J K action Q next 0 0 hold prev Q 01 r e s e t 0 10 s e t 1 1 1 toggle prev Q when clock is high Figure 2. Level-triggered JK latch, schematic and operation table. One of the most common and useful implementations of the level-trigged JK latch is to combine two latches to form a master-slave flip-flop, as shown in Figure 3. The resulting circuit is edge triggered, passing data to the outputs only on a falling (or rising, depending on circuit construction) clock edge. For more information, see the DM7476 in the
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Lab_3 - ECE 331 Spring 2009 Lab 3 Latches and Registers...

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