amd27512 - “W— AMDH Am27C512 512 Kilobit (64 K x 8-Bit)...

Info iconThis preview shows pages 1–12. Sign up to view the full content.

View Full Document Right Arrow Icon
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 4
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 6
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 8
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 10
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 12
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: “W— AMDH Am27C512 512 Kilobit (64 K x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS I Fast access time — Speed options as fast as 55 ns I Latch-up protected to 100 mA from —1 V to vcc + 1 V I High noise immunity I Low power consumption _ 20 #A typical CMOS standby current I Versatile features for simple interfacing I JEDEc-approved pinout — Both CMOS and TTL input/output compatibility I Single +5 V power supply — Two line control functions I :10% power supply tolerance standard I Staman 28'Pin DIP: PDIP: and 32-Pin PLCC l 100% FlashriteTM programming packages —— Typical programming time of 8 seconds GENERAL DESCRIPTION The Am270512 is a 512-Kbit, ultraviolet erasable pro- grammable read-only memory. It is organized as 64K words by 8 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. Products are available in windowed ceramic DlP packages, as well as plastic one time programmable (OTP) PDIP and PLCC packages. Data can be typically accessed in less than 55 ns, al- lowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus micro- processor system. AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 80 mW in active mode, and 100 ,uW in standby mode. All signals are TTL levels, including programming sig- nals. Bit locations may be programmed singly, in blocks, or at random. The device supports AMD’s Flashrite programming algorithm (100 ,us pulses), re- sulting in a typical programming time of 8 seconds. BLOCK DIAGRAM Output Enable Chip Enable and Prog Logic AO—A1 5 Address Inputs Data Outputs DQO—DQ7 524,288 Bit Cell 08140J-1 Publication# 08140 Rev:J Amendment/+2 Issue Date: June 1, 1999 AMDH PRODUCT SELECTOR GUIDE Family Part Number Speed Options m Am27C512 OE# (E#) Access (ns) 150 200 250 «mm CONNECTION DIAGRAMS Top View DIP PLCC Vcc A14 A13 A8 A9 A11 OE# ((E#)/WP 25 I OE# (G#)Npp A10 23 CE#(E#) OE# (E#) 007 D06 D05 DQ4 DOS 0814OJ-2 0814OJ-3 Notes: 1. JEDEC nomenclature is in parenthesis. 2. Don’t use (DU) for PLCC. PIN DESIGNATIONS LOGIC SYMBOL A0—A15 = Address Inputs OE# (E#) = Chip Enable Input DQO—DQ7 = Data Input/Outputs 8 OE# (G#)Npp = Output Enable Input Program Voltage Input DQO‘DQ7 <i> VCC = VCC Supply Voltage OE# (E#) V33 = Ground , OE# (G#)Npp NC = No Internal Connection 08140J-4 2 Am27C51 2 AMDITI ORDERING INFORMATION UV EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: AM27CS12 -55 D C 5 B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in VOLTAGE TOLERANCE 5 = VCC 135% See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C Commercial (0°C to +70°C) l Industrial (—40°C to +85°C) E = Extended (—55°C to +125°C) PACKAGE TYPE D = 28-Pin Ceramic DIP (CDV028) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am270512 512 Kilobit (64 K x 8—Bit) CMOS UV EPROM Valid Combinations AM27C512—55 DC,DCB DC, DCB, DI, DIB AM27C512-55 vCC = 5.0 v i10% AM270512-70 AM27CS12—90 AM27C512-120 AM27CS12-150 AM27CS12-200 AM27C512-255 VCC = 5.0 v i 5% DC, 008, DI, DIB, DE, DEB DC, DCB, DI, DIB Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am27C512 3 AMDH ORDERING INFORMATION OTP EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: AM27C512 -55 P C 5 B OPTIONAL PROCESSING Blank = Standard Processing VOLTAGE TOLERANCE 5 = V00i5% See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C = Commercial (0°C to +70°C) l = Industrial (—40°C to +85°C) E = Extended (—55°C to +125°C) PACKAGE TYPE P = 28-Pin Plastic DIP (PD 028) J = 32-Pin Plastic Leaded Chip Carrier (PL 032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am270512 512 Kilobit (64 K X 8-Bit) CMOS OTP EPROM Valid combinations Valid Combinations Valid Combinations list configurations planned to be sup- J05, P05 ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and AM270512—55 vCC = 5.0 v i 5% JC, PC AM270512_55 - to check on newly released combinations. vCC=5.o v: 10% AM27C512—70 AM270512-90 AM27C512-120 AM270512-15o JC, PC, JI, PI AM27cs12-2oo AM270512-255 vCC = 5.0 v i 5% 4 Am27C51 2 FUNCTIONAL DESCRIPTION Device Erasure In order to clear all locations of their programmed con- tents, the device must be exposed to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase the device. This dosage can be ob- tained by exposure to an ultraviolet lamp—wavelength of 2537 A—with intensity of 12,000 ,uW/cm2 for 15 to 20 minutes. The device should be directly under and about one inch from the source, and all filters should be removed from the UV light source prior to erasure. Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000 A, such as fluorescent light and sunlight. Although the erasure process happens over a much longer time period, ex- posure to any light source should be prevented for maximum system reliability. Simply cover the package window with an opaque label or substance. Device Programming Upon delivery, or after each erasure, the device has all of its bits in the “ONE”, or HIGH state. “ZEROs” are loaded into the device through the programming pro- cedure. The device enters the programming mode when 12.75 V i 0.25 V is applied to the OE#/Vpp pin, and CE# is at VIL. For programming, the data to be programmed is ap- plied 8 bits in parallel to the data pins. The flowchart in the Programming section of the EPROM Products Data Book (Section 5, Figure 5-1) shows AMD’s Flashrite algorithm. The Flashrite algo- rithm reduces programming time by using a 100 ps pro- gramming pulse and by giving each address only as many pulses to reliably program the data. After each pulse is applied to a given address, the data in that ad- dress is verified. If the data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process is repeated while se- quencing through each address of the device. This part of the algorithm is done at VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at VCC = Vpp = 5.25 V. Please refer to Section 5 of the EPROM Products Data Book for additional programming information and spec- ifications. Program Inhibit Programming different data to multiple devices in par- allel is easily accomplished. Except for CE#, all like in- puts of the devices may be common. A TTL low-level program pulse applied to one device’s CE# input with AMDEI CE#NPP = 12.75 V i 0.25 V, will program that particu- lar device. A high-level CE# input inhibits the other de- vices from being programmed. Program Verify A verification should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE#Npp and CE# at VIL, and Vpp between 12.5 V and 13.0 V. Autoselect Mode The autoselect mode provides manufacturer and de— vice identification through identifier codes on DQO— DQ7. This mode is primarily intended for programming equipment to automatically match a device to be pro— grammed with its corresponding programming algo- rithm. This mode is functional in the 25°C i 5°C ambient temperature range that is required when pro- gramming the device. To activate this mode, the programming equipment must force VH on address line A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from V,._ to VIH (that is, chang- ing the address from 00h to 01h). All other address lines must be held at VIL during the autoselect mode. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. Both codes have odd parity, with DQ7 as the parity bit. Read Mode To obtain data at the device outputs, Chip Enable (CE#) and Output Enable (CE#/Vpp) must be driven low. CE# controls the power to the device and is typi- cally used to select the device. CE#NPP enables the device to output data, independent of device selection. Addresses must be stable for at least tACC—tOE. Refer to the Switching Waveforms section for the timing dia- gram. Standby Mode The device enters the CMOS standby mode when CE# is at Vcc 1 0.3 V. Maximum VCC current is reduced to 100 ,uA. The device enters the TTL-standby mode when CE# is at VIH. Maximum VCC current is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-impedance state, indepen- dent of the CE# input. Output OR-Tieing To accommodate multiple memory connections, a two-line control function provides: I Low memory power dissipation, and I Assurance that output bus contention will not occur. Am27C512 5 AMDN CE# should be decoded and used as the primary de- vice-selecting function, while OE#Npp be made a com- mon connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the out— put pins are only active when data is desired from a particular memory device. System Applications During the switch between active and standby condi- tions, transient current peaks are produced on the ris- MODE SELECT TABLE Program Inhibit VIH Autoselect (Note 3) Notes: 1. VH= 12.0 Vi 0.5 V. 2. X: Either V/H OI' V/L. 3. A1—A8 andA10—15 = V,L 4. See DC Programming Characteristics for Vpp voltage during programming. _“nm Manufacturer Code VIL ing and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. At a minimum, a 0.1 ,uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM ar- rays, a 4.7 ,uF bulk electrolytic capacitor should be used between VCC and V33 for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. 6 Am27C512 ABSOLUTE MAXIMUM RATINGS Storage Temperature OTP Products . . . . . . . . . . . . . . . . . . —65°C to +125°C All Other Products . . . . . . . . . . . . . . -65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . ~55°C to +125°C Voltage with Respect to VSS (Note 1) All pins except A9, Vpp, VCC . . —0.6 V to VCC + 0.6 V A9 and Vpp (Note 2) . . . . . . . . . . . . .—0.6 V to 13.5 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . V to V Notes: 1. Minimum DC voltage on input or l/O pins «0.5 V. During voltage transitions, the input may overshoot V53 to —2.0 V for periods of up to 20 ns. Maximum DC voltage on input and //O pins is Vac-+0.5 V. During voltage transi- tions, input and l/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on A9 is —0.5 V. During voltage transitions, A9 and Vpp may overshoot V53 to —2.0 V for periods of up to 20 ns. A9 and Vpp must not exceed + 13.5 V at any time. Stresses above those listed under "Absolute Maximum Fiat- ings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure of the device to absolute maximum ratings for extended periods may affect device reliability. Am27C512 AMDEI OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . .-40°C to +85°C Extended (E) Devices Ambient Temperature (TA) . . . . . . . .—55°C to +125°C Supply Read Voltages VCC for i 5% devices . . . . . . . . . . +4.75 V to +5.25 V VCC for i 10% devices . . . . . . . . . +4.50 V to +5.50 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. AMDI‘J DC CHARACTERISTICS over operating range (unless otherwise specified) Parameter Symbol Parameter Description Test Conditions V Output HIGH Voltage 2.4 Output LOW Voltage V V V V input HIGH Voltage V OH OL IH lL ILI I Output Leakage Current VCC Active Current (Note 2) VCC TTL Standby Current VOUT = O V to VCC . [IA - CE# = VIL,f=10 MHZ, IOUT = 0 mA 25 mA 1 .0 mA vcccmossmdbymm aghvmiosv - Caution: The device must not be removed from (or inserted into) a socket when Vcc or Vpp is applied. Notes: 1. VCC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp 2. ICC, is tested with OE# = VIH to simulate open outputs. 3. Minimum DC Input Voltage is —0.5 V. During transitions, the inputs may overshoot to ~20 V for periods less than 20 ns. Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns. 30 IIIIIIIII l"'i I!!!-.-I 1 2 3 7 8 9 1O 4 5 6 10 Frequency in MHz 25 20 Supply Current in mA 08140J-5 Figure 1. Typical Supply Current vs. Frequency VCC = 5.5 V, T = 25°C 30 # 25 C 9 8E 20 2‘ c m- a) 15 ‘ m IIIIl--. —75 —50 —55 0 25 50 75 100125150 Temperature in °C 0814OJ-6 Figure 2. Typical Supply Current vs. Temperature VCC = 5.5 V, f = 10 MHz 8 Am27C51 2 AMDH TEST CONDITIONS Table 1. Test Specifications Output Load 1 TTL gate Output Load Capaeltance, CL 30 100 pF (Including jig capacrtance) lnput Rise and Fall Times a lnput Pulse Levels 0.0—3.0 0.45—2.4 Input timing measurement 1'5 0‘8, 2.0 V reference levels Output tlmrng measurement 15 0.8, 2.0 V reference levels Note: Diodes are IN3064 or equivalents. 08140J-7 Figure 3. Test Setup SWITCHING TEST WAVEFORM 3V 2.4V 2.0 V 2.0 V > Test Points 4 0.8 V 0.8 V <-~ Test Points —> 0 V 0.45 V Input Output Input Output Note: For CL = 30 pF. Note: For CL = 100 pF. 08140J-8 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS — Center Line is High Impedance State (High 2) KSOOOO‘I O-PAL Am27C51 2 9 AMDZ'I AC CHARACTERISTICS Parameter Symbols Am27C512 JEDEC Standard Description tAVQV Address to Output Delay 200 250 tELQV tCE Chip Enable to Output Delay 55 tGLQV tOE Output Enable to Output Delay CE#:VIL 75 75 t t Chip Enable High or Output tEHQZ (N03: 2) Enable High to Output High 2, Max 25 25 25 30 30 30 30 GHQZ Whichever Occurs First Output Hold Time from tAXQX tOH Addresses, CE# or CE#, Whichever Occurs First Caution: Do not remove the device from (or insert it into) a socket or board that has Vpp or VCC applied. Notes: 1. VCC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp 2. This parameter is sampled and not 100% tested. 3. Switching characteristics are over operating range, unless otherwise specified. 4. See Figure 3 and Table 1 for test specifications. SWITCHING WAVEFORMS 2.4 _ __ _. _ Addresses 3g Addresses Valid ' 0.45 ' _ _ _ _- CE# <— tCE —> CE# ._ _ __ __ tDF (Note 2) <—tOE—> (N tic?) to” High 2 0 e v ' — — — Output Valid Output \\\\\ _ _ __ _ 081 4OJ-9 Notes: 1. CE# may be delayed up to tACC —- tog after the falling edge of the addresses without impact on tACC. 2. tDF is specified from OE# or CE#, whichever occurs first. PACKAGE CAPACITANCE CDV028 PL 032 Parameter Parameter Symbol Description Test Conditions Typ Input Capacitance 10 Output Capacitance 10 Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +2500, f: 1 MHz. 10 Am270512 AMDH PHYSICAL DIMENSIONS* CDV028—28—Pin Ceramic Dual ln-Line Package, UV Lens (measured in inches) DATUM D CENTER PLANE INDEx AND TERMINAL NO. 1 ID. AREA TOP VIEW DATUM D CENTER PLANE 1 435 1 490 ' i .160 BASE PLANE 151i .2?) SEATING PLANE .W . f .300 BSC‘>‘ .005 MIN 045 J .600 ‘ 2m BSC .w .014 .100 BSC . 18 .556 SIDE VIEW END VIEW 16-000038H-3 CDv028 DF10 3-30—95 ae * For reference only. BSC is an ANSI standard for Basic Space Centering. PD 028—28-Pin Plastic Dual ln-Line Package (measured in inches) -M .015 16-038-SB-AG PD 028 DG75 7-13-95 ae SEATING PLANE Am27C512 11 AMDL‘I PHYSICAL DIMENSIONS PL 032—32—Pin Plastic Leaded Chip Carrier (measured in inches) TOP VIEW SEATING PLANE .056 1 6-038FPO-5 PL 032 DA79 6-28—94 ae SIDE VIEW REVISION SUMMARY FOR AM27C512 Revision | (May 1998) Global Changed formatting to match current data sheets. Product Selector Guide Added the -55 speed option for VCC = 5.0 V i 10%. Ordering Information—UV EPROM Products Valid Combinations: -55 speed option added. Combi- nations DI and DIB added for -70 and -90 speed op- tions. Ordering Information—OTP EPROM Products Valid Combinations: Added Speed options for —55 with VCC = V i 50/0 and ‘55 VCC = V i1OO/o. Trademarks Copyright © 1999 Advanced Micro Devices, Inc. All rights reserved. Revision J (January 1999) Ordering Information Added the 5% voltage tolerance information for order- ing part numbers. Revision J+1 (March 5, 1999) Ordering Information UV EPROM Products: Corrected the first row valid combination to D05. Revision J+2 (June 1, 1999) Ordering Information Corrected device organization to 64K x 8-Bit. Absolute Maximum Ratings Changed Note 1 reference to indicate that it pertains voltage on all pins. Corrected Note 1 to indicate that maximum input voltage is VCC+O.5 V. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Flashrite is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 12 Am27C51 2 ...
View Full Document

Page1 / 12

amd27512 - “W— AMDH Am27C512 512 Kilobit (64 K x 8-Bit)...

This preview shows document pages 1 - 12. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online