ABSTRACT This report presents a design of a 3-bit Flash Analog-to-digital converter. The design utilizes a resistor ladder for generating reference voltages, comparator array and an encoder. The comparator was implemented by designing a high gain amplifier. One way to perform the code conversion from Thermometer code to Binary code is using a Priority Encoder. An alternate method was selected which requires very less area and thus drawing very less power from supply. This encoder is a ROM based encoder. The design is aimed to achieve a speed of 40 mega-samples per second. The hand calculations for transistor sizes used are discussed in the report. Simulations were done on CADENCE. Layouts are drawn using 0.25um CMOS technology. Finally, the layout versus simulation (LVS) is performed and post layout simulations are carried out for verification. The total area of the layout is 333.6um × 617.75um. 1
TABLE OF CONTENTS 1.Introduction 3 2.Characteristics of ADC 3 2.1 Quantization Error 4 2.2 Dynamic Range 4 2.3 Differential Nonlinearity 4 2.4 Integral Nonlinearity 4 2.5 Signal-to-Noise ratio 4 2.6 Offset and Gain 5 3. Flash Analog to Digital Converter 3.1 ADC Architecture 5 3.2 Principle of Operation 5 4. Designing the ADC 4.1 Design Specification 6 4.2 Resistor String 6 4.3 Comparator Design 7 4.4 Inverter Design 9 4.5 NAND gate Design 12 4.6 Complete Comparator circuit 13 4.7 Decoder 4.7.1 Logic Block 21 4.7.2 Encoder Circuit 22 4.8 Complete ADC 25 4.9 DNL and INL 31 4.10 ADC Transfer Characteristics 35 5. Applications 35 6. Results 36 7. References 37 8. Appendix 382
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