partial adder design

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Unformatted text preview: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ----------------------------------------------------------------------------------- Company: CSUN -- Engineer: HARSHIT JARIWALA --- Create Date: 20:29:28 09/13/2009 -- Design Name: PARTIAL ADDER -- Module Name: partialadder - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity partialadder is Port ( ai : in STD_LOGIC; bi : in STD_LOGIC; cin : in STD_LOGIC; cgi : out STD_LOGIC; cpi : out STD_LOGIC; sum : out STD_LOGIC); end partialadder; architecture Behavioral of partialadder is begin sum<=ai xor bi xor cin; cgi<=ai and bi; cpi<=ai xor bi; end Behavioral; ...
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  • Fall '09
  • proframinroosta
  • Harshad number, Prime number, Xilinx primitives, HARSHIT JARIWALA, architecture Behavioral of partialadder, PARTIAL ADDER

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