{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

carry look ahed adder design

carry look ahed adder design - 1 2 3 4 5 6 7 8 9 10 11 12...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 ----------------------------------------------------------------------------------- Company: CSUN -- Engineer: HARSHIT JARIWALA --- Create Date: 20:17:00 09/13/2009 -- Design Name: CARRY LOOK AHEAD ADDER -- Module Name: lookahead - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity lookahead is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); cin : in STD_LOGIC; s : out STD_LOGIC_VECTOR (3 downto 0); cout : out STD_LOGIC); end lookahead; architecture Behavioral of lookahead is signal g,p :std_logic_vector (3 downto 0); signal c :std_logic_vector (4 downto 0); component partialadder is port(ai,bi,cin:in std_logic; sum,cgi,cpi:out std_logic ); end component; begin c(0)<=cin; c(1)<=(p(0) and cin) or g(0); c(2)<=(cin and p(0) and p(1)) or (g(0) and p(1)) or g(1); c(3)<=(cin and p(0) and p(1) and p(2)) or (g(0) and p(1) and p(2)) or (g(1) and p(2)) or g(2); c(4)<=(cin and p(0) and p(1) and p(2) and p(3)) or (g(0) and p(1) and p(2) and p(3)) or (g(1) and p(2) and p(3)) or (g(2) and p(3)) or g(3); cout<= c(4); 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 u1: u2: u3: u4: partialadder partialadder partialadder partialadder port port port port map(a(0),b(0),c(0),s(0),g(0),p(0)); map(a(1),b(1),c(1),s(1),g(1),p(1)); map(a(2),b(2),c(2),s(2),g(2),p(2)); map(a(3),b(3),c(3),s(3),g(3),p(3)); end Behavioral; ...
View Full Document

  • Spring '09
  • proframinroosta
  • Prime number, architecture Behavioral of lookahead, partialadder partialadder partialadder, port port port

{[ snackBarMessage ]}

Page1 / 3

carry look ahed adder design - 1 2 3 4 5 6 7 8 9 10 11 12...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon bookmark
Ask a homework question - tutors are online