seqdetect with overlap

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Unformatted text preview: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 ----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 14:37:49 09/15/2009 -- Design Name: SEQUENCE DETECTER WITH OVERLAPPING -- Module Name: seq_detect - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity seq_detect is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; q : out STD_LOGIC); end seq_detect; architecture Behavioral of seq_detect is type state is (s0,s1,s2,s3,s4,s5,s6); signal pr_state,nx_state:state; begin process (rst,clk) begin if (rst='1') then pr_state <= S0; elsif (clk'event and clk='1') then pr_state <= nx_state; end if; end process; process (d,pr_state) begin case pr_state is when s0=> q<= '0'; if (d='1') then nx_state <= s1; else nx_state <=s4; end if; when s1=> q<= '0'; if (d='1') then nx_state <= s2; 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 else nx_state <=s4; end if; when s2=> q<= '0'; if (d='1') then nx_state <= s3; else nx_state <=s4; end if; when s3=> q<= '1'; if (d='1') then nx_state <= s3; else nx_state <=s4; end if; when s4=> q<= '0'; if (d='1') then nx_state <= s1; else nx_state <=s5; end if; when s5=> q<= '0'; if (d='1') then nx_state <= s1; else nx_state<=s6; end if; when s6=> q<= '1'; if (d='1') then nx_state <= s1; else nx_state <=s6; end if; end case; end process; end Behavioral; ...
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seqdetect with overlap - 1 2 3 4 5 6 7 8 9 10 11 12 13 14...

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