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seqdetect without overlap

seqdetect without overlap - 1 2 3 4 5 6 7 8 9 10 11 12 13...

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1 ---------------------------------------------------------------------------------- 2 -- Company: 3 -- Engineer: 4 -- 5 -- Create Date: 15:32:19 09/15/2009 6 -- Design Name: SEQUENCE DETECTER WITHOUT OVERLAPPING 7 -- Module Name: seq_detec_2 - Behavioral 8 -- Project Name: 9 -- Target Devices: 10 -- Tool versions: 11 -- Description: 12 -- 13 -- Dependencies: 14 -- 15 -- Revision: 16 -- Revision 0.01 - File Created 17 -- Additional Comments: 18 -- 19 ---------------------------------------------------------------------------------- 20 library IEEE; 21 use IEEE.STD_LOGIC_1164. ALL ; 22 use IEEE.STD_LOGIC_ARITH. ALL ; 23 use IEEE.STD_LOGIC_UNSIGNED. ALL ; 24 25 ---- Uncomment the following library declaration if instantiating 26 ---- any Xilinx primitives in this code. 27 --library UNISIM; 28 --use UNISIM.VComponents.all; 29 30 entity seq_detec_2 is 31 Port ( d : in STD_LOGIC ; 32 clk : in STD_LOGIC ; 33 rst : in STD_LOGIC ; 34 q : out STD_LOGIC ); 35 end seq_detec_2; 36 37 architecture Behavioral of seq_detec_2 is 38 39 type state is (s0,s1,s2,s3,s4,s5,s6); 40 signal pr_state,nx_state:state; 41 42 begin 43 process (rst,clk) 44 begin 45
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