EE660Hw2-Fall09-Correction3

EE660Hw2-Fall09-Correction3 - EE 660 Homework 2 Fall 2009...

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Unformatted text preview: EE 660 Homework 2 Fall 2009 Correction 2 Due: Wed September 30, 2009 Problem 1 [6 pts]. This is in regards to Appendix A and especially Appendix A.3. Recall that Figure A.19 (page A‐32) describes the operation of the 5‐stage pipelined MIPS, Figure A.21 (page A‐34) describes stalls with respect to the LW instruction, and Figure A.22 (page A‐36) describes how forwarding is implemented. Also recall that the instructions discussed were • Register‐register ALU (or Reg‐Reg‐ALU) such as ADD or SUB. These are R‐type instructions. • ALU‐immediate (or ALU‐imm) such as ADDI. These are I‐type instructions. • Load word (LW). These are I‐type instructions. • Store word (SW). These are I‐type instructions. • Branch (BR). These are I‐type instructions. Recall that the R‐type and I‐type instruction formats are as follows: R‐type op rs rt rd shamt funct I‐type op rs rt imm For the R‐type instruction, op = opcode field, rs = source register, rt = second source register, rd = destination register, funct = function field, and shamt = you can ignore this and assume it’s zero. For example, add $rd,$rs,$rt For the I‐type instructions ALU‐imm and SW, op = opcode field, rs = source register, rt = destination register, and imm = immediate constant. For example, lw $rt,imm($rs), sw $rt,imm($rs), or addi $rt,$rs,imm For the I‐type instruction SW, op = opcode field, rs = source register, rt = register to store, and imm = immediate constant. For example, lw $rt,imm($rs). For the I‐type instruction BR, op = opcode field, rs = one register, rt = the other register, and imm = offset. For example, beq $r1,$r2,Label (= PC+4 + offset) We would like to implement forwarding for the 5‐stage pipelined MIPS. This requires defining the control of the two multiplexers at the inputs of the ALU as shown in Figure A.23 (page A‐37). Note that the top and bottom multiplexers have five possible inputs. ALU Inputs Top ALU Input Possible multiplexer inputs ID/EX.A (top output of register file) ID/EX.ALUOutput (output of the ALU) EX/MEM.ALUOutput (output of the ALU) MEM/WB.LMD Note that there is a fifth input but we’ll ignore it ID/EX.B (bottom output of register file) ID/EX.Imm (sign extended constant) ID/EX.ALUOutput (output of the ALU) EX/MEM.ALUOutput (output of the ALU) MEM/WB.LMD Figure 1. ALU input possibilities. Now let’s review what the ALU does for each type of instruction: • Load and store: the ALU is used to compute the sum of register rs and the constant “imm”. • Reg‐reg‐ALU: the ALU is used to compute using the two operands from registers rs and rt. • ALU‐Imm: the ALU adds the register rs with the constant “imm”. • Branch: the ALU computes the target branch address by adding register rs with “imm”. Figure A.22 explains how the inputs of the ALU are controlled. The following is a pseudo C language description of the bottom input of the ALU. Note that the possible values of the bottom input are shown in Figure 1. Recall that the register rd field in an instruction format is different for the R and I type instructions. In the description below, we won’t worry about this and assume that the hardware can figure this out by examining the opcode field. Bottom ALU Input if (ID/EX.IR[op] == Reg‐reg‐ALU) { // Case: two consecutive Reg‐reg ALU instructions if ((EX/MEM.IR[op] == Reg‐reg‐ALU) and (EX/MEM.IR[rd] == ID/EX.IR[rt])) { Bottom ALU input = EX/MEM.ALUOutput; } // Case: Reg‐reg ALU instruction following ALU‐imm instruction else if ((EX/MEM.IR[op] ==ALU‐imm) and (EX/MEM.IR[rt] == ID/EX.IR[rt])) { Bottom ALU input = EX/MEM.ALUOutput; } // Note that there is no case of Reg‐reg‐ALU instruction following LW due to Fig. A.21 // Case: Reg‐reg ALU instructions with one bubble else if ((MEM/WB.IR[op] == Reg‐reg‐ALU) and (MEM/WB.IR[rd] == ID/EX.IR[rt])) { Bottom ALU input = EX/MEM.ALUOutput; } // Case: Reg‐reg ALU instruction following a bubble then ALU‐imm instruction else if ((MEM/WB.IR[op] == ALU‐imm) and (MEM/WB.IR[rt] == ID/EX.IR[rt])) { Bottom ALU input = MEM/WB.ALUOutput; } // Case: Reg‐reg ALU instruction following a bubble then LW instruction else if ((MEM/WB.IR[op] == LW) and (MEM/WB.IR[rt] == ID/EX.IR[rt])) { Bottom ALU input = MEM/WB.LMD; } } else if (ID/EX.IR[op] == ALU‐imm or LW or SW or BR) { Bottom ALU input = ID/EX.imm; } For this problem, write a pseudo C language description of the top input of the ALU. The following problems are from another textbook by the same authors, “Computer Organization and Design: The Hardware/Software Inteface”, fourth edition. Problem 2 [4 pts]. This exercise refers to the following loop. Assume that perfect branch prediction is used (no stalls due to control hazards), that there are no delay slots (i.e., bubbles), and that the pipeline has full forwarding support. Also assume that many iterations of this loop are executed before the loop exits. Assume the pipeline MIPS shown in Figure A.18 (page A‐31) with the modifications, similar as shown in Figure A.23 (page A.37), to support full forwarding. Loop: lw $1,40($6) add $5,$5,$8 add $6,$6,$8 sw $1,20($5) beq $1,$0,Loop How often (as a percentage of all clock cycles) do we have a cycle in which all five pipeline stages are doing useful work? (Hint: draw the pipeline under different scenarios, e.g., when lw is in the last stage, when add $5,$5,$8 is in the last stage, etc, and cases when there is a bubble in the last stage). Problem 3. Consider the following instruction sequence lw $1,40($2) add $2,$3,$3 add $1,$1,$2 sw $1,20($2) (a) [2 pts] Find all data dependencies in this instruction sequence. (b) [2 pts] Find all hazards in this instruction sequence for the 5‐stage pipelined MIPS (c) [2 pts] To reduce clock cycle time, suppose the MEM stage is split into two stages. Now find all hazards in this instruction sequence of a 6‐stage pipelined MIPS. Problem 4. This problem is intended to help you understand the relationship between forwarding, hazard detection, and ISA design. The computer is assumed to be the 5‐stage pipelined MIPS. Consider the following instruction sequence: lw $1,40($6) add $2,$3,$1 add $1,$6,$4 sw $2,20($4) and $1,$1,$4 Comment: the “and” is a bit‐wise “and” operation. It is an R‐type instruction, similar to “add”. (a) [2 pts] If there is no forwarding or hazard detection, insert nops to ensure correct execution (recall, nops are instructions that do nothing). (b) [2 pts] Repeat Problem 4(a) but now use nops only when a hazard cannot be avoided by changing or rearranging these instructions. You can assume register R7 can be used to hold temporary values in your modified code. (c) [2 pts] If the processor has forwarding, but we forget to implement the hazard detection unit, what happens when this code executes? (Recall that the hazard detection unit any potential hazards and insert stalls or bubbles to avoid errors.) ...
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This note was uploaded on 10/01/2009 for the course EE 660 taught by Professor Sasaki during the Spring '09 term at Hawaii.

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