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chapter7-MemoryHierarchy-partA-cache_organization-Fall2008-final

Chapter7-MemoryHierarchy-partA-cache_organization-Fall2008-final

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Processor Processor-Memory (DRAM) Memory (DRAM) ∆ιαφορά επίδοσης P μProc 60%/yr ance 10000 forma 100 1000 Processor-Memory Performance Gap: (grows 50% / year) Perf 1 10 DRAM 7%/yr. 1980 1981 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 1982 2001 2002 2003 2004 2005 [email protected] 2008-2009 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
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Ιεραρχία μνήμης Part of The On-chip CPU Datapath 16-256 Registers Όσο απομακρυνόμαστε από τη CPU : Μικρότερο κόστος /Bit 16 256 One or more levels (Static RAM): Level 1: On-chip 16-64K Level 2: On or Off-chip 128-512K Registers C h Μεγαλύτερη χωρητικότητα Μεγαλύτερος χρόνος πρόσβασης καθυστέρηση Level 3: Off-chip 128K-8M Cache Main Memory πρόσβασης - καθυστέρηση Χαμηλότερος ρυθμός εξόδου Dynamic RAM (DRAM) 16M 16G Magnetic Disc 16M-16G Interface: SCSI, RAID, IDE 1394 Optical Disk or Magnetic Tape IDE, 1394 4G-100G [email protected] 2008-2009
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Παράδειγμα Ιεραρχίας Μνήμης ( με 2 επίπεδα cache ) Μεγαλύτερη Ταχύτητα Μεγαλύτερη Χωρητικότητα C l Vi t l Processor Control Virtual Memory, Secondary Storage R Main Memory Second Level Tertiary Storage (Tape) On-Chip Datapath (Disk) Registers (DRAM) Cache (SRAM) L 2 On Chip Level One Cache L 1 1-5ns 10ms Ταχύτητα : 10ns 50ns <1KB >1GB Μέγεθος : <256KB <4GB 10sec TB 30ns <8MB [email protected] 2008-2009 150GB/s 10MB/s Bandwidth : 50GB/s 4GB/s 25GB/s
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Το μοντέλο της Ιεραρχίας Μνήμης Di k Disk memory μέγεθος : 500bytes 64KB 512MB 100GB ταχύτητα : 0,25ns 1ns 100ns 5ms [email protected] 2008-2009
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Παράδειγμα Ιεραρχίας μνήμης Digital PWS 600 au Digital PWS 600 au - Alpha 21164 CPU Alpha 21164 CPU – 600MHz 600MHz CPU Level Capacity Throughput Latency 32 registers Register 512B 24GB/sec 2ns 1000W L1 cache 12000W L2 cache L1 cache 8KB 16GB/sec 2ns L2 cache 96KB 8GB/sec 6ns 0.5MW ext.L3 cache L3 cache 4MB 888MB/sec 24ns 64MW main memory 1GW Disk space Main Mem 512MB 1GB/sec 112ns [email protected] 2008-2009
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Τυπικές Αρχιτεκτονικές IBM Power 3: • L1 = 64 KB, 128-way set associative L2 4 MB di d li i 128 i b k • L2 = 4 MB, direct mapped, line size = 128, write back Compaq EV6 (Alpha 21264): • L1 = 64 KB 2 way associative line size= 32 • L1 = 64 KB, 2-way associative, line size= 32 • L2 = 4 MB (or larger), direct mapped, line size = 64 HP PA: no L2 • PA8500, PA8600: L1 = 1.5 MB • PA8700: L1 = 2.25 MB AMD Athlon: L1 = 64 KB, L2 = 256 KB Intel Pentium 4: L1 = 8 KB, L2 = 256 KB Intel Itanium: • L1 = 16 KB, 4-way associative L2 96 KB 6 i ti [email protected] 2008-2009 • L2 = 96 KB, 6-way associative • L3 = off chip, size varies
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Γιατί είναι ωφέλιμη η Ιεραρχία Μνήμης ; ό έ (d l l d ) Τοπικότητα δεδομένων (data locality data locality) Κατά κανόνα τα προγράμματα προσπελαύνουν ένα μικρό μόνο μέρος του συνόλου των διευθύνσεων ( εντολές / δεδομένα ) κατά την εκτέλεση ενός συγκεκριμένου τμήματός τους ∆ύο
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