Lab 4 Writeup - Albert Ho ECE 315 Tuesday lab Lab 04...

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Albert Ho ECE 315 Tuesday lab Lab 04 writeup Objective: The purpose of this lab was to examine the MOSFET and CMOS inverter characteristics. Topics covered in this laboratory included measuring the IV characteristic and extracting the model parameter for a MOS Field-Effect Transistor. We examined the CMOS inverter transfer characteristics (V in vs. V out ). We then used load-line analysis to find from the VTC the parameter values needed for analysis. Finally we examined and made comparisons on different inverter topologies, finding the propagation delays and voltage gains of different types of CMOS inverters. PSPICE was used for simulation in this lab. Equipment: PSPICE software (use of program’s Mbreakn model for simulation) PC – Keithley CTrace software, Metratek Waveform Manager Pro 2 Keithley SMU’s (Source Measurement Units) - denotation: SMU1 is for sweeping, and SMU2 is for stepping ALD1116PA MOSFET (contains 2 nMOSFETs, with shared bulk voltage) ALD1117PA MOSFET (contains 2 pMOSFETs, with shared bulk voltage) 100 nF capacitor, 10 kΩ resistor Breadboard + associated wires SPECIAL NOTE: Lab TAs explicitly advised us not to do parts 2.0 and 7.0, so the lab writeup for these sections are not necessary Experimental Results: Transistor Transfer Curves in nMOSFETs The setup procedure involved placing an ALD1116PA MOSFET onto the breadboard and wiring the drain to a DC 2.5 V power supply. We also grounded the source and bulk, and connected the gate to a sweeping SMU. We ran the Keithley CTrace software to receive the data while sweeping the gate to source voltage of the nMOSFET from 0 V to 2.5 V, in increments of 20 mV. The following is a plot of drain current I D vs. gate bias V GS :
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Figure A : Plot of I D vs. V GS for nMOSFET We then examined the case when the bulk to source is biased. Running the same experiment above with the same stepping of V GS while keeping V DS constant at 2.5 V, except this time biasing the bulk to source at V BS = -1 and V BS = -3 V afterward, we obtain the following plots of drain current I D versus gate to source voltage V GS Figure B : Plot of I D vs. V GS for nMOSFET for applied V BS = -1 V
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Figure C : Plot of I D vs. V GS for nMOSFET for applied V BS = -3 V Since a good picture of the nMOSFET transistor behavior can be formulated from examining a graph of drain current and drain to source voltage, we stepped the gate to source voltage from V GS = 0.5 V to V GS = 10.5 V in 2.5 V steps while sweeping the drain voltage from V DS = 0 V to V DS = 10 V. The following is a plot of drain current I D vs. drain to source bias V DS , while stepping V GS : Figure D : Plot of I D vs. V DS for nMOSFET (family of IV curves for various steps of V GS ) In order to see the backgate effect, we now examine the case when the bulk to source is biased. We obtain the IV curves for V BS = -1 V and V BS = -3 V. Running the
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same experiment as above for obtaining the I D vs. V DS curves , we obtain new plots of I
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This lab report was uploaded on 09/23/2007 for the course ECE 3150 taught by Professor Spencer during the Spring '07 term at Cornell University (Engineering School).

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Lab 4 Writeup - Albert Ho ECE 315 Tuesday lab Lab 04...

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