1647590108 - 045 R Spartan-II 2.5V FPGA Family Functional...

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DS001-2 (v2.2) September 3, 2003 www.xilinx.com Module 2 of 4 Product Specification 1-800-255-7778 1 © 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm . All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. Architectural Description Spartan-II Array The Spartan-II user-programmable gate array, shown in Figure 1 , is composed of five major configurable elements: IOBs provide the interface between the package pins and the internal logic CLBs provide the functional elements for constructing most logic Dedicated block RAM memories of 4096 bits each Clock DLLs for clock-distribution delay compensation and clock domain control Versatile multi-level interconnect structure As can be seen in Figure 1 , the CLBs form the central logic structure with easy access to all support and routing struc- tures. The IOBs are located around all the logic and mem- ory elements for easy and quick routing of signals on and off the chip. Values stored in static memory cells control all the config- urable logic elements and interconnect resources. These values load into the memory cells on power-up, and can reload if necessary to change the function of the device. Each of these elements will be discussed in detail in the fol- lowing sections. Input/Output Block The Spartan-II IOB, as seen in Figure 1 , features inputs and outputs that support a wide variety of I/O signaling stan- dards. These high-speed inputs and outputs are capable of supporting various state of the art memory and bus inter- faces. Table 1 lists several of the standards which are sup- ported along with the required reference, output and termination voltages needed to meet the standard. The three IOB registers function either as edge-triggered D-type flip-flops or as level-sensitive latches. Each IOB has a clock signal (CLK) shared by the three registers and inde- pendent Clock Enable (CE) signals for each register. 045 Spartan-II 2.5V FPGA Family: Functional Description DS001-2 (v2.2) September 3, 2003 00 Product Specification R Figure 1: Spartan-II Input/Output Block (IOB) Package Pin Package Pin D CK EC SR Q Programmable Bias & ESD Network V CCO I/O I/O, V REF Internal Reference To Next I/O To Other External V Inputs of Bank Input Buffer Output Buffer Delay VCC OE O OCE I ICE IQ CLK TCE T DS001_02_090600 TFF OFF IFF
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Spartan-II 2.5V FPGA Family: Functional Description Module 2 of 4 www.xilinx.com DS001-2 (v2.2) September 3, 2003 2 1-800-255-7778 Product Specification R In addition to the CLK and CE control signals, the three reg- isters share a Set/Reset (SR). For each register, this signal can be independently configured as a synchronous Set, a synchronous Reset, an asynchronous Preset, or an asyn- chronous Clear.
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1647590108 - 045 R Spartan-II 2.5V FPGA Family Functional...

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