60292-Chapter_08

60292-Chapter_08 - CHAPTER 8 Exercises E8.1 The number of...

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CHAPTER 8 Exercises E8.1 The number of bits in the memory addresses is the same as the address bus width, which is 20. Thus the number of unique addresses is 2 20 = 1,048,576 = 1024 × 1024 = 1024K. E8.2 (8 bits/byte) × (64 Kbytes) = 8 × 64 × 1024 = 524,288 bits E8.3 Because D is a double byte register, two bytes of memory are needed to store its content. Starting from the initial situation shown in Figure 8.9a in the book, execution of the command PSHD results in: 0907: SP 0908: 0909: 34 090A: A2 Then the PULX command reads two bytes from the stack and we have: 0907: X: 34A2 0908: 0909: 34 SP 090A: A2 E8.4 Starting from the initial situation shown in Figure 8.9a in the book, execution of the command PSHD results in: 0907: SP 0908: 0909: 34 090A: A2 Then the command PSHA results in: SP 0907: 0908: 34 0909: 34 090A: A2 286
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Next the PULX command reads two bytes from the stack and we have: 0907: X: 3434 0908: 34 SP 0909: 34 090A: A2 E8.5 The results are given in the book. E8.6 (a) LDAA $0202 This instruction uses extended addressing. The effective address is 0202. In Figure 8.11 we see that this location contains 1A. Thus the content of the A register after this instruction is 1A. (b) LDAA #$43 This instruction uses immediate addressing. The effective address is the one immediately following the op code. This location contains the hexadecimal digits 43. Thus the content of the A register after this instruction is 43. (c) LDAA $05,X This instruction uses indexed addressing. The effective address is the content of the X register plus the offset which is 05. Thus the effective address is 0205. In Figure 8.11 we see that this location contains FF. Thus the content of the A register after this instruction is FF. (d) LDAA $06 This instruction uses direct addressing. The effective address is 0006. In Figure 8.11 we see that this location contains 13. Thus the content of the A register after this instruction is 13. (e) LDAA $07,X This instruction uses indexed addressing. The effective address is the content of the X register plus the offset which is 07. Thus the effective address is 2007. In Figure 8.11 we see that this location contains 16. Thus the content of the A register after this instruction is 16. 287
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E8.7 (a) Referring to Table 8.1 in the book, we see that CLRA is the clear accumulator A instruction with a single byte op code 4F. Furthermore execution of this command sets the Z bit of the condition code register. The BEQ $15 command occupies two memory locations with the op code 27 in the first byte and the offset of 15 in the second byte. Thus starting in location 0200, the instructions appear in memory as: 0200: 4F 0201: 27 0202: 14 (b) When the instructions are executed, the CLRA command sets the Z bit. Then if the Z-bit was clear the next instruction would be the one starting in location 0203 following the BEQ $15 command. However since the Z bit is set the next instruction is located at 0203 + 15 = 0218. E8.8
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This note was uploaded on 10/08/2009 for the course AERO 215 taught by Professor Tyler during the Spring '09 term at Texas A&M.

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60292-Chapter_08 - CHAPTER 8 Exercises E8.1 The number of...

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