EEE466_L08, 9 & 10

EEE466_L08, 9 & 10 - Classifying ISA's General ISA...

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Wed. and Fri. Based in part th Edition Classifying ISA’s General ISA Organization Operand characteristics – How are operands stored in the CPU? How many operands are in an instruction? Memory characteristics Endianness and Alignment Instructions Addressing modes supported – how is data address specified? ALU operations – what functions are performed by atomic instructions Control operations – branch architecture Instruction encoding How do we encode instructions as a sequence of 0’s and 1’s
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Wed. and Fri. Based in part th Edition Familiar Example: HCS12 b Register Set: Figure 3-1 from the HCS12 Core User Guide
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Wed. and Fri. Based in part th Edition HCS12 Addressing Modes b Inherent s No operands or all operands are in registers B INX (increments the X register) B TAB (transfer A to B) B ABA (A A + B) b Immediate s Operand is included in the instruction itself; 8 or 16 bit with length determined by context B LDAA #5A (load the A register with 5A hex) B LDX #3AFF (load the X register with 3AFF hex)
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Wed. and Fri. Based in part th Edition HCS12 Addressing Modes b Direct s Data operand is the contents of the location at the low order 8 bits of an address in the range 0000 – FFFF B LDAA $C5 (load A with contents of location C5) b Extended s Data operand is the contents of the location at a 16- bit address B STAA $6DFF (store A in location 6DFF)
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Wed. and Fri. Based in part th Edition HCS12 Addressing Modes b Relative s Address of the operand is the value in PC when the instruction is executed plus an 8 or 16-bit offset that is part of the instruction b Indexed s Address of the operand is found by adding or subtracting a value from X, Y, SP, or PC B There are 8 variations of Indexed mode: s Simplest: address = Reg + offset, and the offset can be 5-bit, 8- bit, or 16-bit s LDAA $FF, X (load A with what is at (X)+FF) s STAA $A000, Y (store A in (Y) + A000)
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Wed. and Fri. Based in part th Edition HCS12 Addressing Modes b Indexed (the other 5 variations) s Predecrement s Preincrement s Postdecrement s Postincrement s Accumulator Offset These form the address of the operand by pre incrementing or decrementing X, Y or SP by 1 to 8 These use the value in X, Y, or SP as the address of the operand then post incrementing or decrementing X, Y or SP by 1 to 8 The address of the operand is formed by adding the value in X, Y, SP, or PC to the value in A, B, or D
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Wed. and Fri. Based in part th Edition HCS12 Addressing Modes b Indexed Indirect s With 16-bit offset – the address of the data is found
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This note was uploaded on 10/11/2009 for the course EE 466 taught by Professor Conry during the Spring '09 term at Clarkson University .

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EEE466_L08, 9 & 10 - Classifying ISA's General ISA...

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