chapter5(a) [Compatibility Mode]

chapter5(a) [Compatibility Mode] - EE141 Digital Integrated...

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EE141 1 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan © Digital Integrated Circuits 2nd Inverter The Inverter Borivoje Nikolic DIGITAL GATES Fundamental Parameters ± Functionality ± Reliability, Robustness ± Area © Digital Integrated Circuits 2nd Inverter ± Performance ² DC Characteristics ² Speed (delay) ² Power Consumption Noise in Digital Integrated Circuits V DD v ( t ) i ( t ) © Digital Integrated Circuits 2nd Inverter (a) Inductive coupling (b) Capacitive coupling ( c) Power and ground noise The Ideal Gate V out R i = © Digital Integrated Circuits 2nd Inverter V in g= −∞ i R o = 0
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EE141 2 CMOS Inverter First Order DC Analysis V OL = 0 V OH = V DD V DD V DD R p © Digital Integrated Circuits 2nd Inverter V M = f(R n , R p ) V in = V DD V in = 0 V out V out R n Mapping between analog and digital signals "1" V OH V IH V(y) V OH Slope = -1 © Digital Integrated Circuits 2nd Inverter "0" V IL V OL Undefined Region V(x) V OL V IH V IL Slope = -1 Definition of Noise Margins V IH "1" V OH NM H Noise Margin High © Digital Integrated Circuits 2nd Inverter V IL Undefined Region "0" V OL NM L Gate Output Gate Input Noise Margin Low The Regenerative Property (a) A chain of inverters. v 1 , v 3 , . .. v 1 , v 3 , . .. v0 v 1 v 2 v 3 v 4 v5 v6 . . © Digital Integrated Circuits 2nd Inverter v 0 , v 2 , . .. v 0 , v 2 , . .. (b) Regenerative gate f(v) finv(v) finv(v) f(v) (c) Non-regenerative gate
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EE141 3 Fan in and Fan out M (a) Fan-out N © Digital Integrated Circuits 2nd Inverter N (b) Fan-in M The CMOS Inverter: A First Glance V V V DD © Digital Integrated Circuits 2nd Inverter in out C L CMOS Inverter V DD PMOS 2 λ Ou In V DD PMOS Contacts N Well © Digital Integrated Circuits 2nd Inverter Polysilicon In Out GND Metal 1 NMOS Out NMOS VTC of Real Inverter 30 4.0 5.0 ) NM L © Digital Integrated Circuits 2nd Inverter 0.0 1.0 2.0 3.0 4.0 5.0 V in (V) 1.0 2.0 3.0 V out (V) V M NM H
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EE141 4 CMOS Inverter: Transient Response t pHL = f(R on .C L ) = 0.69 R on C L V R p DD © Digital Integrated Circuits 2nd Inverter out n in = = 0 (a) Low-to-high (b) High-to-low C L Delay Definitions t V in 50% © Digital Integrated Circuits 2nd Inverter t pHL t pLH t V out 50% t r 10% 90% t f Ring Oscillator v 0 v 1 v 2 v 3 v 4 v 5 © Digital Integrated Circuits 2nd Inverter v0 v 1 v5 T = 2 × t p × N Power Dissipation © Digital Integrated Circuits 2nd Inverter
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EE141 5 Voltage Transfer © Digital Integrated Circuits 2nd Inverter Characteristic CMOS Inverter V DD PMOS 2 λ Ou In V DD PMOS Contacts N Well © Digital Integrated Circuits 2nd Inverter Polysilicon In Out GND Metal 1 NMOS Out NMOS DC Operation: Voltage Transfer Characteristic V(y) V OH f V(y)=V(x) V(y) V(x) dVo/dVi =-1 NML © Digital Integrated Circuits 2nd Inverter V(x) V OL V LT V OH V OL Switching Logic Threshold Nominal Voltage Levels VIL VIH NMH CMOS Inverter Ou In V DD PMOS Vsg Vsd Vgs(n) = Vin Vsg(p) = Vdd Vin © Digital Integrated Circuits 2nd Inverter Out NMOS Vgs Vds Vsg(p) = Vdd – Vin Vds(n) = Vout Vsd(p) = Vdd -Vout
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EE141 6 CMOS Inverter Load Characteristics I n,p V in = 0 PMOS © Digital Integrated Circuits 2nd Inverter NMOS V in = 0 Vout
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This note was uploaded on 10/11/2009 for the course ECE 141 taught by Professor Staff during the Spring '09 term at Alabama A&M University.

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chapter5(a) [Compatibility Mode] - EE141 Digital Integrated...

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