Lecture 4 Verilog HDL with Synthesis

Lecture 4 Verilog HDL with Synthesis - EE 577B Lecture # 4:...

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EE 577B EE 577B Lecture # 4: Lecture # 4: Verilog HDL With Synthesis Verilog HDL With Synthesis Perspective Perspective Dr. Rashed Zafar Bhatti
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2 Lecture Outline Lecture Outline z Fundamentals of Verilog HDL z Verilog Coding Styles and Logic inferences z Logic inferences and mapping ± Combination Logic ± Registers ± Latches !! z Logic Synthesis z Non-Synthesizable and Synthesizable constructs of Verilog z Dos and Donts of Verilog Coding z Implementing a Finite State Machine (FSM) z Using Synopsys Design Compiler
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3 Fundamentals of Verilog HDL Fundamentals of Verilog HDL z Module z Data Type z Basic Constructs ± Primitives ± Continues or concurrent assignments ± Procedural blocks: always @ (…) ² Level Sensitive ² Edge Sensitive ± Procedural assignments ² Blocking ² Non Blocking z Coding Styles ± Structural ± Dataflow ± RTL (A.K.A Behavioral RTL)
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4 Module Module z Basic unit of description in Verilog is the module z A module describes ± Functionality or structure of a design ± Ports through which it connects with other modules z Modules provide the mechanism for hierarchical designs ± A module may be instantiated within another modules module Top wire Sbus C1 : module Child reg Art task Proc reg Art block BLB reg Art
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5 Module Syntax Module Syntax module module_name ( port_list ) port declarations: input , output , inout , reg internal declarations: reg, wire, parameter, function, task, … Statements: initial, always, module instantiation, gate instantiation, continuous assignment endmodule z Example module HA (A, B, S, C); input A, B; output S, C; assign S = A ^ B; assign C = A & B; endmodule
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6 Two Main Data Types Two Main Data Types z Nets represent connections between things ± Do not hold their value ± Take their value from a driver such as a gate or other module ± Cannot be assigned in an initial or always block z Regs represent data storage ± Behave exactly like memory in a computer ± Hold their value until explicitly assigned in an initial or always block ± Never connected to something ± Can be used to model wires, latches, flip-flops, etc., but do not correspond exactly ± Shared variables with all their attendant problems
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7 Four Four - - valued Data valued Data z Verilog’s nets and registers hold four-valued data z 0, 1 ± Obvious z Z ± Output of an undriven tri-state driver ± Models case where nothing is setting a wire’s value z X ± Models when the simulator can’t decide the value ± Initial state of registers ± When a wire is being driven to 0 and 1 simultaneously ± Output of a gate with Z inputs
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8 Four Four - - valued Logic valued Logic z Logical operators work on three-valued logic 01X Z 00000 101X X X0 XXX Z0 Output 0 if one input is 0 Output X if both inputs are gibberish
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9 Gate Gate - - level Primitives level Primitives z Verilog provides the following: and nand logical AND/NAND or nor logical OR/NOR xor xnor logical XOR/XNOR buf not buffer/inverter bufif0 notif0 Tristate with low enable bifif1 notif1 Tristate with high enable z Example module mux(f, a, b, sel); output f; input a, b, sel; and
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This note was uploaded on 10/12/2009 for the course EE 577B taught by Professor Bhatti during the Fall '08 term at USC.

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Lecture 4 Verilog HDL with Synthesis - EE 577B Lecture # 4:...

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